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/gem5/ext/sst/tests/
H A Dtest6_arm_4c.py191 comp_dirctrl = sst.Component("dirctrl", "memHierarchy.DirectoryController") variable
192 comp_dirctrl.addParams({
202 sst.Link("link_dir_net_0").connect((comp_chiprtr, "port1", "2ns"), (comp_dirctrl, "network", "2ns"))
204 sst.Link("link_dir_mem_link").connect((comp_dirctrl, "memory", "10ns"), (memory, "direct_link", "10ns"))

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