Searched refs:MISCREG_ICH_LR0 (Results 1 - 3 of 3) sorted by relevance

/gem5/src/arch/arm/
H A Dmiscregs.hh861 MISCREG_ICH_LR0, enumerator in enum:ArmISA::MiscRegIndex
H A Dmiscregs.cc778 return MISCREG_ICH_LR0;
4893 InitReg(MISCREG_ICH_LR0)
4926 .mapsTo(MISCREG_ICH_LR0)
/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc709 case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15:
1489 case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: {

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