Searched refs:MISCREG_ICH_AP0R0_EL2 (Results 1 - 4 of 4) sorted by relevance

/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc626 case MISCREG_ICH_AP0R0_EL2:
1572 case MISCREG_ICH_AP0R0_EL2:
1743 RegVal vapr0 = isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i);
1755 isa->setMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i, vapr0);
1869 MISCREG_ICH_AP0R0_EL2 + reg_no : MISCREG_ICH_AP1R0_EL2 + reg_no;
2193 isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i) |
/gem5/src/arch/arm/
H A Dmiscregs.hh726 MISCREG_ICH_AP0R0_EL2, enumerator in enum:ArmISA::MiscRegIndex
H A Disa.cc742 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
2079 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
H A Dmiscregs.cc2481 return MISCREG_ICH_AP0R0_EL2;
4674 InitReg(MISCREG_ICH_AP0R0_EL2)

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