Searched refs:MISCREG_ICC_IGRPEN1_EL1 (Results 1 - 3 of 3) sorted by relevance

/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc186 case MISCREG_ICC_IGRPEN1_EL1: {
191 value = readBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1);
1348 case MISCREG_ICC_IGRPEN1_EL1: {
1353 setBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1, val);
/gem5/src/arch/arm/
H A Dmiscregs.hh717 MISCREG_ICC_IGRPEN1_EL1, enumerator in enum:ArmISA::MiscRegIndex
H A Dmiscregs.cc2457 return MISCREG_ICC_IGRPEN1_EL1;
4648 InitReg(MISCREG_ICC_IGRPEN1_EL1)

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