Searched refs:MISCREG_ICC_CTLR_EL1 (Results 1 - 3 of 3) sorted by relevance

/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc558 case MISCREG_ICC_CTLR_EL1: {
563 value = readBankedMiscReg(MISCREG_ICC_CTLR_EL1);
1129 case MISCREG_ICC_CTLR_EL1: {
1144 readBankedMiscReg(MISCREG_ICC_CTLR_EL1);
1202 setBankedMiscReg(MISCREG_ICC_CTLR_EL1, icc_ctlr_el1);
/gem5/src/arch/arm/
H A Dmiscregs.hh710 MISCREG_ICC_CTLR_EL1, enumerator in enum:ArmISA::MiscRegIndex
H A Dmiscregs.cc2451 return MISCREG_ICC_CTLR_EL1;
4618 InitReg(MISCREG_ICC_CTLR_EL1)

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