Searched hist:2010 (Results 1 - 25 of 929) sorted by relevance
/gem5/src/arch/arm/insts/ | ||
H A D | mult.hh | 7158:195780d97b1b Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Add base classes for multiply instructions. |
/gem5/src/arch/arm/isa/decoder/ | ||
H A D | thumb.isa | diff 7732:a2c660de7787 Mon Nov 08 14:58:00 EST 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add support for M5 ops in the ARM ISA diff 7639:8c09b7ff5b57 Wed Aug 25 20:10:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement all ARM SIMD instructions. diff 7435:62bdb68bb314 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode the neon instruction space. diff 7433:b812790a16eb Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Move some case values out of ##included files. This will help keep the high level decode together and not have it spread into the subordinate decode stuff. The ##include lines still need to be on a line by themselves, though. diff 7363:3b3b3325140c Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Move the VFP data operation decode into a function. diff 7340:cd78c8367084 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Fix up thumb decoding of coproc instructions. diff 7339:be7111fd22d9 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Clean up some redundancy and fault behavior for unimplemented thumb MCR, MRC. diff 7321:d0fdf3452086 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode 8, 16, and 32 bit transfers between core and extension (fp) registers. diff 7293:a907ebdb7ee9 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode the RFE instruction. diff 7281:e67b0c646268 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: When an instruction is intentionally undefined, fault on it. |
H A D | arm.isa | diff 7732:a2c660de7787 Mon Nov 08 14:58:00 EST 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add support for M5 ops in the ARM ISA diff 7433:b812790a16eb Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Move some case values out of ##included files. This will help keep the high level decode together and not have it spread into the subordinate decode stuff. The ##include lines still need to be on a line by themselves, though. diff 7418:e81194228b6e Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Move some miscellaneous instructions out of the decoder to share with thumb. diff 7407:70f65d4c7fe3 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Get rid of some of the old FP implementation. diff 7401:9b873c0357b8 Wed Jun 02 01:58:00 EDT 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add BKPT instruction diff 7400:f6c9b27c4dbe Wed Jun 02 01:58:00 EDT 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Implement ARM CPU interrupts diff 7363:3b3b3325140c Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Move the VFP data operation decode into a function. diff 7350:41e3ee23125e Wed Jun 02 01:58:00 EDT 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add some support for wfi/wfe/yield/etc diff 7344:82a4e24e7fad Wed Jun 02 01:58:00 EDT 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: BXJ should be BX when there is no J support diff 7334:5e8dcb57096f Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Make VFP load/store and 64 bit move decode correspond with CP10 and CP11. |
/gem5/src/arch/x86/regs/ | ||
H A D | apic.hh | 7629:0f0c231e3e97 Mon Aug 23 19:14:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Create a directory for files that define register indexes. This is to help tidy up arch/x86. These files should not be used external to the ISA. |
/gem5/src/arch/arm/isa/formats/ | ||
H A D | data.isa | diff 7602:cd1930acae4e Mon Aug 23 12:18:00 EDT 2010 Gene Wu <Gene.Wu@arm.com> ARM: BX instruction can be contitional if last instruction in a IT block Branches are allowed to be the last instuction in an IT block. Before it was assumed that they could not. So Branches in thumb2 were Uncond. diff 7432:7501a6d33e3e Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Combine some redundant cases in one of the data decode functions. diff 7419:10e7f0f18461 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Hook the misc instructions into the thumb decoder. diff 7418:e81194228b6e Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Move some miscellaneous instructions out of the decoder to share with thumb. diff 7410:1589cdca3c6e Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement the bkpt instruction. diff 7408:ee6949c5bb5b Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR. diff 7316:bb190cb8ee69 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode the CPS instruction. diff 7308:d70cc65e9bc8 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode the setend instruction. diff 7290:ea9189fbb84f Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Make sure some undefined thumb32 instructions fault. diff 7258:6e8a3c0a2a40 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode the bfi and bfc instructions. |
H A D | uncond.isa | diff 7605:94b2f78894ca Mon Aug 23 12:18:00 EDT 2010 Gene Wu <Gene.Wu@arm.com> ARM: Implement DSB, DMB, ISB diff 7603:66d853e566d2 Mon Aug 23 12:18:00 EDT 2010 Gene Wu <Gene.Wu@arm.com> ARM: Implement CLREX diff 7602:cd1930acae4e Mon Aug 23 12:18:00 EDT 2010 Gene Wu <Gene.Wu@arm.com> ARM: BX instruction can be contitional if last instruction in a IT block Branches are allowed to be the last instuction in an IT block. Before it was assumed that they could not. So Branches in thumb2 were Uncond. diff 7499:be7c22eb8c20 Thu Jul 15 05:11:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Make an SRS instruction with a bad mode cause an undefined instruction fault. diff 7435:62bdb68bb314 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode the neon instruction space. diff 7421:9962b65e6b1f Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Make sure undefined unconditional ARM instructions decode as such. diff 7359:c1ed3d411971 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode ARM unconditional MRC and MCR instructions. diff 7357:0c08f7a95f19 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode the unconditional version of ARM fp instructions. diff 7316:bb190cb8ee69 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode the CPS instruction. diff 7314:f254f66afb11 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode the SRS instruction. |
H A D | mult.isa | diff 7319:d4e9a5e31a38 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement the udiv instruction. diff 7318:64352bcff9f3 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement the sdiv instruction. diff 7290:ea9189fbb84f Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Make sure some undefined thumb32 instructions fault. diff 7243:d503503b3966 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode the usad8 and usada8 instructions. diff 7162:97fe2d298f3e Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Remove special naming for the new version of multiply. 7161:a1e9b36bd4bf Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Hook the new multiply instructions into all the decoders. |
/gem5/src/cpu/testers/memtest/ | ||
H A D | SConscript | 7632:acf43d6bbc18 Tue Aug 24 03:07:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> testers: move testers to a new directory This patch moves the testers to a new subdirectory under src/cpu and includes the necessary fixes to work with latest m5 initialization patches. |
/gem5/src/arch/arm/isa/ | ||
H A D | copyright.txt | diff 7091:050e5e2aa89f Wed Jun 02 01:57:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Remove IsControl from operands that don't imply control transfers. Also remove IsInteger from CondCodes. |
/gem5/src/arch/sparc/ | ||
H A D | microcode_rom.hh | diff 7741:340b6f01d69b Thu Nov 11 05:03:00 EST 2010 Gabe Black <gblack@eecs.umich.edu> SPARC: Clean up some historical style issues. |
/gem5/src/arch/x86/isa/insts/general_purpose/arithmetic/ | ||
H A D | __init__.py | diff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly |
/gem5/src/arch/x86/isa/insts/general_purpose/compare_and_test/ | ||
H A D | __init__.py | diff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly |
H A D | compare.py | diff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly |
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/ | ||
H A D | __init__.py | diff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly |
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/ | ||
H A D | __init__.py | diff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly |
/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/ | ||
H A D | __init__.py | diff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly |
/gem5/src/arch/x86/isa/insts/general_purpose/flags/ | ||
H A D | __init__.py | diff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly |
/gem5/src/arch/x86/isa/insts/general_purpose/input_output/ | ||
H A D | __init__.py | diff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly |
/gem5/src/arch/x86/isa/insts/general_purpose/ | ||
H A D | load_effective_address.py | diff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly |
/gem5/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/ | ||
H A D | __init__.py | diff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly |
/gem5/src/arch/x86/isa/insts/general_purpose/string/ | ||
H A D | __init__.py | diff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly |
/gem5/src/arch/x86/isa/insts/simd128/ | ||
H A D | __init__.py | diff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly |
/gem5/src/arch/x86/isa/insts/simd128/floating_point/ | ||
H A D | __init__.py | diff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly |
/gem5/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/ | ||
H A D | __init__.py | diff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly |
H A D | horizontal_subtraction.py | diff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly |
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