Searched hist:13396 (Results 1 - 7 of 7) sorted by relevance
| /gem5/src/systemc/tests/ | ||
| H A D | verify.py | diff 13333:1c8ced831e21 Wed Oct 10 22:03:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Stop filtering out warnings about unimplemented features. These no longer cause any of the tests to break, so there's no reason to filter them out. Change-Id: I9c0b25fc42eb3060ac7d6d6a46ded130227c302d Reviewed-on: https://gem5-review.googlesource.com/c/13396 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
| /gem5/src/arch/arm/ | ||
| H A D | system.hh | diff 13396:23277eaae855 Wed Oct 31 13:12:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: ArmSystem::resetAddr64 renamed to be used in AArch32 ARMv8 differs from ARMv7 with the presence of RVBAR register, which contains the implementation defined reset address when EL3 is not implemented. The entry 0x0 in the AArch32 vector table, once used for the Reset Vector, is now marked as "Not used", stating that it is now IMPLEMENTATION DEFINED. An implementation might still use this vector table entry to hold the Reset vector, but having a Reset address != than the general vector table (for any other exception) is allowed. At the moment any Reset exception is still using 0 as a vector table base address. This patch is extending the ArmSystem::resetAddr64 to ArmSystem::resetAddr so that it can be used for initializing MVBAR/RVBAR. In order to do so, we are providing a specialized behavior for the Reset exception when evaluating the vector base address. Change-Id: I051a730dc089e194db3b107bbed19251c661f87e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14000 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | system.cc | diff 13396:23277eaae855 Wed Oct 31 13:12:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: ArmSystem::resetAddr64 renamed to be used in AArch32 ARMv8 differs from ARMv7 with the presence of RVBAR register, which contains the implementation defined reset address when EL3 is not implemented. The entry 0x0 in the AArch32 vector table, once used for the Reset Vector, is now marked as "Not used", stating that it is now IMPLEMENTATION DEFINED. An implementation might still use this vector table entry to hold the Reset vector, but having a Reset address != than the general vector table (for any other exception) is allowed. At the moment any Reset exception is still using 0 as a vector table base address. This patch is extending the ArmSystem::resetAddr64 to ArmSystem::resetAddr so that it can be used for initializing MVBAR/RVBAR. In order to do so, we are providing a specialized behavior for the Reset exception when evaluating the vector base address. Change-Id: I051a730dc089e194db3b107bbed19251c661f87e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14000 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | faults.hh | diff 13396:23277eaae855 Wed Oct 31 13:12:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: ArmSystem::resetAddr64 renamed to be used in AArch32 ARMv8 differs from ARMv7 with the presence of RVBAR register, which contains the implementation defined reset address when EL3 is not implemented. The entry 0x0 in the AArch32 vector table, once used for the Reset Vector, is now marked as "Not used", stating that it is now IMPLEMENTATION DEFINED. An implementation might still use this vector table entry to hold the Reset vector, but having a Reset address != than the general vector table (for any other exception) is allowed. At the moment any Reset exception is still using 0 as a vector table base address. This patch is extending the ArmSystem::resetAddr64 to ArmSystem::resetAddr so that it can be used for initializing MVBAR/RVBAR. In order to do so, we are providing a specialized behavior for the Reset exception when evaluating the vector base address. Change-Id: I051a730dc089e194db3b107bbed19251c661f87e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14000 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | ArmSystem.py | diff 13396:23277eaae855 Wed Oct 31 13:12:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: ArmSystem::resetAddr64 renamed to be used in AArch32 ARMv8 differs from ARMv7 with the presence of RVBAR register, which contains the implementation defined reset address when EL3 is not implemented. The entry 0x0 in the AArch32 vector table, once used for the Reset Vector, is now marked as "Not used", stating that it is now IMPLEMENTATION DEFINED. An implementation might still use this vector table entry to hold the Reset vector, but having a Reset address != than the general vector table (for any other exception) is allowed. At the moment any Reset exception is still using 0 as a vector table base address. This patch is extending the ArmSystem::resetAddr64 to ArmSystem::resetAddr so that it can be used for initializing MVBAR/RVBAR. In order to do so, we are providing a specialized behavior for the Reset exception when evaluating the vector base address. Change-Id: I051a730dc089e194db3b107bbed19251c661f87e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14000 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | faults.cc | diff 13396:23277eaae855 Wed Oct 31 13:12:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: ArmSystem::resetAddr64 renamed to be used in AArch32 ARMv8 differs from ARMv7 with the presence of RVBAR register, which contains the implementation defined reset address when EL3 is not implemented. The entry 0x0 in the AArch32 vector table, once used for the Reset Vector, is now marked as "Not used", stating that it is now IMPLEMENTATION DEFINED. An implementation might still use this vector table entry to hold the Reset vector, but having a Reset address != than the general vector table (for any other exception) is allowed. At the moment any Reset exception is still using 0 as a vector table base address. This patch is extending the ArmSystem::resetAddr64 to ArmSystem::resetAddr so that it can be used for initializing MVBAR/RVBAR. In order to do so, we are providing a specialized behavior for the Reset exception when evaluating the vector base address. Change-Id: I051a730dc089e194db3b107bbed19251c661f87e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14000 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | isa.cc | diff 13396:23277eaae855 Wed Oct 31 13:12:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: ArmSystem::resetAddr64 renamed to be used in AArch32 ARMv8 differs from ARMv7 with the presence of RVBAR register, which contains the implementation defined reset address when EL3 is not implemented. The entry 0x0 in the AArch32 vector table, once used for the Reset Vector, is now marked as "Not used", stating that it is now IMPLEMENTATION DEFINED. An implementation might still use this vector table entry to hold the Reset vector, but having a Reset address != than the general vector table (for any other exception) is allowed. At the moment any Reset exception is still using 0 as a vector table base address. This patch is extending the ArmSystem::resetAddr64 to ArmSystem::resetAddr so that it can be used for initializing MVBAR/RVBAR. In order to do so, we are providing a specialized behavior for the Reset exception when evaluating the vector base address. Change-Id: I051a730dc089e194db3b107bbed19251c661f87e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14000 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
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