Searched hist:12640 (Results 1 - 3 of 3) sorted by relevance
| /gem5/src/arch/arm/insts/ | ||
| H A D | branch.cc | 12640:02188fc84bae Tue Mar 27 12:31:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Fix AArch32 branch instructions disassemble This patch adds the generateDisassembly method for BranchReg, BranchImm and BranchRegReg Base classes used by AArch32 branch instructions. Change-Id: I6de015cc213335556d5187df3d4fcd765876262c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9503 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | branch.hh | diff 12640:02188fc84bae Tue Mar 27 12:31:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Fix AArch32 branch instructions disassemble This patch adds the generateDisassembly method for BranchReg, BranchImm and BranchRegReg Base classes used by AArch32 branch instructions. Change-Id: I6de015cc213335556d5187df3d4fcd765876262c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9503 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/arch/arm/ | ||
| H A D | SConscript | diff 12640:02188fc84bae Tue Mar 27 12:31:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Fix AArch32 branch instructions disassemble This patch adds the generateDisassembly method for BranchReg, BranchImm and BranchRegReg Base classes used by AArch32 branch instructions. Change-Id: I6de015cc213335556d5187df3d4fcd765876262c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9503 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
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