Searched hist:10622 (Results 1 - 4 of 4) sorted by relevance
/gem5/src/mem/cache/ | ||
H A D | mshr_queue.hh | diff 10622:0b969a35781f Tue Dec 23 09:31:00 EST 2014 Mitch Hayenga <mitch.hayenga@arm.com> mem: Add parameter to reserve MSHR entries for demand access Adds a new parameter that reserves some number of MSHR entries for demand accesses. This helps prevent prefetchers from taking all MSHRs, forcing demand requests from the CPU to stall. |
H A D | mshr_queue.cc | diff 10622:0b969a35781f Tue Dec 23 09:31:00 EST 2014 Mitch Hayenga <mitch.hayenga@arm.com> mem: Add parameter to reserve MSHR entries for demand access Adds a new parameter that reserves some number of MSHR entries for demand accesses. This helps prevent prefetchers from taking all MSHRs, forcing demand requests from the CPU to stall. |
H A D | base.cc | diff 12729:9870d6f73e04 Wed May 30 18:09:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Fix secure bit modification Secure bit was being updated outside insertion. Change-Id: I83d9b010e8cf64013bbea9bae3ea68b0c414a189 Reviewed-on: https://gem5-review.googlesource.com/10622 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> diff 10622:0b969a35781f Tue Dec 23 09:31:00 EST 2014 Mitch Hayenga <mitch.hayenga@arm.com> mem: Add parameter to reserve MSHR entries for demand access Adds a new parameter that reserves some number of MSHR entries for demand accesses. This helps prevent prefetchers from taking all MSHRs, forcing demand requests from the CPU to stall. |
H A D | cache.cc | diff 12729:9870d6f73e04 Wed May 30 18:09:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Fix secure bit modification Secure bit was being updated outside insertion. Change-Id: I83d9b010e8cf64013bbea9bae3ea68b0c414a189 Reviewed-on: https://gem5-review.googlesource.com/10622 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
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