| /gem5/src/arch/arm/ |
| H A D | stage2_mmu.hh | 93 void setVirt(Addr vaddr, int size, Request::Flags flags, int masterId) function in class:ArmISA::Stage2MMU::Stage2Translation
96 req->setVirt(0, vaddr, size, flags, masterId, 0);
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| H A D | stage2_mmu.cc | 71 req->setVirt(0, descAddr, numBytes, flags | Request::PT_WALK, masterId, 0);
106 translation->setVirt(
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| H A D | stage2_lookup.hh | 86 req->setVirt(0, s1Te.pAddr(s1Req->getVaddr()), s1Req->getSize(),
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| H A D | isa.cc | 2004 req->setVirt(0, val, 0, flags, Request::funcMasterId,
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| /gem5/src/cpu/simple/ |
| H A D | atomic.cc | 356 req->setVirt(0, frag_addr, frag_size, flags, dataMasterId(),
363 req->setVirt(0, frag_addr, frag_size, flags, dataMasterId(),
598 req->setVirt(0, addr, size, flags, dataMasterId(),
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| H A D | base.cc | 480 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH,
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| /gem5/src/mem/ |
| H A D | request.hh | 318 * paddr is written via setVirt() or setPhys(), so it is always
467 setVirt(asid, vaddr, size, flags, mid, pc);
475 setVirt(asid, vaddr, size, flags, mid, pc, std::move(atomic_op));
529 setVirt(uint64_t asid, Addr vaddr, unsigned size, Flags flags, function
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| /gem5/src/cpu/o3/ |
| H A D | lsq.hh | 460 setVirt(int asid, Addr vaddr, unsigned size, Request::Flags flags_, function
463 request()->setVirt(asid, vaddr, size, flags_, mid, pc);
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| /gem5/src/cpu/minor/ |
| H A D | lsq.cc | 494 fragment->setVirt(0 /* asid */,
505 fragment->setVirt(0 /* asid */,
1635 request->request->setVirt(0 /* asid */,
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| H A D | fetch1.cc | 172 request->request->setVirt(0 /* asid */,
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| /gem5/src/cpu/checker/ |
| H A D | cpu_impl.hh | 252 mem_req->setVirt(0, fetch_PC, sizeof(MachInst),
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| /gem5/src/cpu/ |
| H A D | base.cc | 334 req->setVirt(0, addr, size, 0x0, dataMasterId(), tc->instAddr());
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| /gem5/src/arch/arm/tracers/ |
| H A D | tarmac_parser.cc | 1056 req->setVirt(0, addr, size, flags, thread->pcState().instAddr(),
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| /gem5/src/cpu/trace/ |
| H A D | trace_cpu.cc | 665 req->setVirt(node_ptr->asid, node_ptr->virtAddr, node_ptr->size,
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