Searched refs:table (Results 1 - 25 of 36) sorted by relevance

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/gem5/src/mem/slicc/symbols/
H A DAction.py31 def __init__(self, table, ident, resources, location, pairs):
32 super(Action, self).__init__(table, ident, location, pairs)
H A DTransition.py32 def __init__(self, table, machine, state, event, nextState, actions,
35 super(Transition, self).__init__(table, ident, location)
H A DFunc.py32 def __init__(self, table, ident, name, location, return_type, param_types,
34 super(Func, self).__init__(table, ident, location, pairs)
H A DStateMachine.py59 self.table = None
103 assert self.table is None
107 assert self.table is None
111 assert self.table is None
130 assert self.table is None
134 assert self.table is None
141 # register func in the symbol table
167 # Needs to be called before accessing the table
169 assert self.table is None
171 table
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/gem5/src/arch/x86/
H A Dsystem.cc213 * 4 entry which points to one page directory pointer table which
220 // Put valid values in all of the various table entries which indicate
242 for (int table = 0; table < NumPDTs; table++) {
243 pdpe = X86ISA::htog(0x7 | PageDirTable[table]);
244 physProxy.writeBlob(PageDirPtrTable + table * 8, &pdpe, 8);
251 for (int table = 0; table < NumPDTs; table
301 Addr fixed, table; local
314 writeOutSMBiosTable(Addr header, Addr &headerSize, Addr &structSize, Addr table) argument
332 writeOutMPTable(Addr fp, Addr &fpSize, Addr &tableSize, Addr table) argument
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H A Dsystem.hh99 Addr &headerSize, Addr &tableSize, Addr table = 0);
102 Addr &fpSize, Addr &tableSize, Addr table = 0);
H A Dpagetable.hh88 // A bit used to form an index into the PAT table.
137 // Unfortunately, the placement of the base field in a page table entry is
172 read(PortProxy &p, Addr table, Addr vaddr) argument
174 entryAddr = table;
/gem5/src/base/
H A Dinifile.cc49 SectionTable::iterator i = table.begin();
50 SectionTable::iterator end = table.end();
83 EntryTable::iterator ei = table.find(entryName);
85 if (ei == table.end()) {
87 table[entryName] = new Entry(value);
129 EntryTable::const_iterator ei = table.find(entryName);
131 return (ei == table.end()) ? NULL : ei->second;
138 SectionTable::iterator i = table.find(sectionName);
140 if (i != table.end()) {
146 table[sectionNam
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H A Dinifile.hh50 /// It's basically a two level lookup table: a set of named sections,
98 EntryTable table; ///< Table of entries. member in class:IniFile::Section
104 : table(), referenced(false)
111 /// Add an entry to the table. If an entry with the same name
118 /// Add an entry to the table given a string assigment.
145 SectionTable table; member in class:IniFile
/gem5/src/arch/mips/
H A Dtlb.cc66 table = new PTE[size];
67 memset(table, 0, sizeof(PTE[size]));
73 if (table)
74 delete [] table;
87 PTE *pte = &table[index];
113 return &table[Index];
125 PTE *pte = &table[index];
173 if (table[Index].V0 || table[Index].V1) {
175 PageTable::iterator i = lookupTable.find(table[Inde
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H A Dtlb.hh61 PageTable lookupTable; // Quick lookup into page table
63 MipsISA::PTE *table; // the Page Table member in class:MipsISA::TLB
/gem5/src/arch/power/
H A Dtlb.cc70 table = new PowerISA::PTE[size];
71 memset(table, 0, sizeof(PowerISA::PTE[size]));
77 if (table)
78 delete [] table;
91 PowerISA::PTE *pte = &table[index];
116 return &table[Index];
128 PowerISA::PTE *pte = &table[index];
169 if (table[Index].V0 || table[Index].V1) {
172 PageTable::iterator i = lookupTable.find(table[Inde
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/gem5/src/arch/riscv/
H A Dtlb.cc68 table = new PTE[size];
69 memset(table, 0, sizeof(PTE[size]));
75 if (table)
76 delete [] table;
89 PTE *pte = &table[index];
115 return &table[Index];
127 PTE *pte = &table[index];
175 if (table[Index].V0 || table[Index].V1) {
177 PageTable::iterator i = lookupTable.find(table[Inde
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H A Dtlb.hh60 PageTable lookupTable; // Quick lookup into page table
62 RiscvISA::PTE *table; // the Page Table member in class:RiscvISA::TLB
/gem5/src/dev/storage/
H A Ddisk_image.cc184 : DiskImage(p), filename(p->image_file), child(p->child), table(NULL)
202 SectorTable::iterator i = table->begin();
203 SectorTable::iterator end = table->end();
276 table = new SectorTable(sector_count);
286 assert(table->find(offset) == table->end());
287 (*table)[offset] = sector;
299 table = new SectorTable(hash_size);
358 SafeWriteSwap(stream, (uint64_t)table->size());
360 uint64_t size = table
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/gem5/src/mem/cache/prefetch/
H A Ddelta_correlating_prediction_tables.cc41 table(p->table_assoc, p->table_entries, p->table_indexing_policy,
136 // Look up table entry, is_secure is unused in findEntry because we
138 DCPTEntry *entry = table.findEntry(pc, false /* unused */);
144 entry = table.findVictim(pc);
146 table.insertEntry(pc, false /* unused */, entry);
H A Ddelta_correlating_prediction_tables.hh104 /** The main table */
105 AssociativeSet<DCPTEntry> table; member in class:DeltaCorrelatingPredictionTables
/gem5/src/arch/alpha/
H A Dtlb.cc67 : BaseTLB(p), table(p->size), nlu(0)
188 TlbEntry *entry = &table[index];
252 if (table[nlu].valid) {
253 Addr oldvpn = table[nlu].tag;
261 if (table[index].tag != oldvpn)
267 DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn);
274 table[nlu] = entry;
275 table[nlu].tag = vaddr.vpn();
276 table[nlu].valid = true;
286 std::fill(table
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H A Dtlb.hh75 PageTable lookupTable; // Quick lookup into page table
77 std::vector<TlbEntry> table; // the Page Table member in class:AlphaISA::TLB
80 void nextnlu() { if (++nlu >= table.size()) nlu = 0; }
92 int getsize() const { return table.size(); }
123 // Most recently used page table entries
/gem5/src/dev/arm/
H A DFlashDevice.py73 of the data in the adress table; Stripe needed for multiple\
/gem5/src/mem/
H A Dmulti_level_page_table.hh33 * Declaration of a multi-level page table.
47 * This class implements an in-memory multi-level page table that can be
50 * to do a normal page table walk.
52 * To reduce memory required to store the page table, a multi-level page
53 * table stores its translations similarly with a radix tree. Let n be
56 * multi-level page table will store its translations at level 0 (the
85 * different levels of the page table.
94 * For every level of the page table, from n to 1, the base address
137 walk(System *system, Addr pageSize, Addr table, Addr vaddr, argument
140 entry->read(system->physProxy, table, vadd
148 walk(System *system, Addr pageSize, Addr table, Addr vaddr, bool allocate, Final *entry) argument
171 walk(System *system, Addr pageSize, Addr table, Addr vaddr, bool allocate, typename LastType<EntryTypes...>::type *entry) argument
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/gem5/ext/systemc/src/sysc/utils/
H A Dsc_hash.cpp22 sc_hash.cpp -- Implementation of a chained hash table with MTF
508 table = t;
513 for (int i = index; i < table->num_bins; ++i) {
514 if (table->bins[i] != 0) {
516 last = &(table->bins[i]);
538 for (int i = index; i < table->num_bins; ++i) {
539 if (table->bins[i] != 0) {
541 last = &(table->bins[i]);
559 --table->num_entries;
570 --table
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/gem5/src/arch/arm/
H A Dtlb.cc77 : BaseTLB(p), table(new TlbEntry[p->size]), size(p->size),
100 delete[] table;
161 if ((!ignore_asn && table[x].match(va, asn, vmid, hyp, secure, false,
163 (ignore_asn && table[x].match(va, vmid, hyp, secure, target_el))) {
167 TlbEntry tmp_entry = table[x];
169 table[i] = table[i - 1];
170 table[0] = tmp_entry;
171 retval = &table[0];
173 retval = &table[
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/gem5/src/sim/
H A DProcess.py47 table in an architecture-specific format')
/gem5/src/arch/arm/linux/
H A Dprocess.cc1656 SyscallTable table; local
1658 table.descs = syscallDescs32;
1659 table.size = sizeof(syscallDescs32) / sizeof(SyscallDesc);
1660 table.base = 0;
1661 syscallTables.push_back(table);
1662 table.base = 0x900000;
1663 syscallTables.push_back(table);
1665 table.descs = privSyscallDescs32;
1666 table.size = sizeof(privSyscallDescs32) / sizeof(SyscallDesc);
1667 table
1675 SyscallTable table; local
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