Searched refs:sram (Results 1 - 6 of 6) sorted by relevance

/gem5/ext/mcpat/cacti/
H A Dsubarray.cc73 area.h = cam_cell.h * (num_rows + 1);//height of subarray is decided by CAM array. blank space in sram array are filled with dummy cells
136 C_wl = (gate_C_pass(g_tp.sram.cell_a_w,
137 (g_tp.sram.b_w - 2 * g_tp.sram.cell_a_w) / 2.0,
140 C_b_row_drain_C = drain_C_(g_tp.sram.cell_a_w, NCH, 1, 0, cell.w, false, true) / 2.0; // due to shared contact
157 C_wl_ram = (gate_C_pass(g_tp.sram.cell_a_w,
158 (g_tp.sram.b_w - 2 *
159 g_tp.sram.cell_a_w) / 2.0, false,
183 //height of subarray is decided by CAM array. blank space in sram array are filled with dummy cells
184 C_b_row_drain_C = drain_C_(g_tp.sram
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H A Dparameter.cc175 sram.display(indent + 2);
330 cell.h = g_tp.sram.b_h + 2 * wire_local.pitch *
333 cell.w = g_tp.sram.b_w + 2 * wire_local.pitch *
341 cell.h = g_tp.sram.b_h + 2 * wire_local.pitch * (g_ip->num_rw_ports - 1 + g_ip->num_rd_ports +
343 cell.w = g_tp.sram.b_w + 2 * wire_local.pitch * (g_ip->num_rw_ports - 1 + g_ip->num_wr_ports +
351 cell.h = g_tp.sram.b_h + 2 * wire_local.pitch * (g_ip->num_wr_ports +
353 cell.w = g_tp.sram.b_w + 2 * wire_local.pitch * (g_ip->num_rw_ports - 1 +
394 double Cbitrow_drain_cap = drain_C_(g_tp.sram.cell_a_w, NCH, 1, 0, cell.w, false, true) / 2.0;
H A Dparameter.h231 MemoryType sram; member in class:TechnologyParameter
266 sram.reset();
H A Dmat.cc499 r_b_metal = cam_cell.h * g_tp.wire_local.R_per_um;//dummy rows in sram are filled in
503 log((g_tp.sram.Vbitpre - 0.1 * dp.V_b_sense) /
504 (g_tp.sram.Vbitpre - dp.V_b_sense)) *
558 log((g_tp.sram.Vbitpre - 0.1 * dp.V_b_sense) /
559 (g_tp.sram.Vbitpre - dp.V_b_sense)) *
1021 // cam and sram have same cell trasistor properties
1022 double R_sram_cell_pull_up_tr = tr_R_on(g_tp.sram.cell_pmos_w, NCH, 1, is_dram, true);
1023 double R_access_tr = tr_R_on(g_tp.sram.cell_a_w, NCH, 1, is_dram, true);
1071 V_b_pre = g_tp.sram.Vbitpre;
1074 R_cell_pull_down = tr_R_on(g_tp.sram
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H A Drouter.cc188 dyn_p.cell.h = g_tp.sram.b_h + 2 * g_tp.wire_outside_mat.pitch * (dyn_p.num_wr_ports +
190 dyn_p.cell.w = g_tp.sram.b_w + 2 * g_tp.wire_outside_mat.pitch * (dyn_p.num_rw_ports - 1 +
H A Dtechnology.cc1704 g_tp.sram.cell_a_w += curr_alpha * curr_Wmemcella_sram;
1705 g_tp.sram.cell_pmos_w += curr_alpha * curr_Wmemcellpmos_sram;
1706 g_tp.sram.cell_nmos_w += curr_alpha * curr_Wmemcellnmos_sram;
1789 g_tp.sram.b_w = sqrt(area_cell_sram / (asp_ratio_cell_sram));
1790 g_tp.sram.b_h = asp_ratio_cell_sram * g_tp.sram.b_w;
1795 g_tp.sram.Vbitpre = vdd[ram_cell_tech_type];

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