Lines Matching refs:sram
499 r_b_metal = cam_cell.h * g_tp.wire_local.R_per_um;//dummy rows in sram are filled in
503 log((g_tp.sram.Vbitpre - 0.1 * dp.V_b_sense) /
504 (g_tp.sram.Vbitpre - dp.V_b_sense)) *
558 log((g_tp.sram.Vbitpre - 0.1 * dp.V_b_sense) /
559 (g_tp.sram.Vbitpre - dp.V_b_sense)) *
1021 // cam and sram have same cell trasistor properties
1022 double R_sram_cell_pull_up_tr = tr_R_on(g_tp.sram.cell_pmos_w, NCH, 1, is_dram, true);
1023 double R_access_tr = tr_R_on(g_tp.sram.cell_a_w, NCH, 1, is_dram, true);
1071 V_b_pre = g_tp.sram.Vbitpre;
1074 R_cell_pull_down = tr_R_on(g_tp.sram.cell_nmos_w, NCH, 1, false, true);
1075 R_cell_acc = tr_R_on(g_tp.sram.cell_a_w, NCH, 1, false, true);
1079 double Iport = cmos_Isub_leakage(g_tp.sram.cell_a_w, 0, 1, nmos,
1081 double Iport_erp = cmos_Isub_leakage(g_tp.sram.cell_a_w, 0, 2, nmos,
1083 double Icell = cmos_Isub_leakage(g_tp.sram.cell_nmos_w,
1084 g_tp.sram.cell_pmos_w, 1, inv, false,
1093 double Ig_port_erp = cmos_Ig_leakage(g_tp.sram.cell_a_w, 0, 1, nmos,
1095 double Ig_cell = cmos_Ig_leakage(g_tp.sram.cell_nmos_w,
1096 g_tp.sram.cell_pmos_w, 1, inv, false,