110152Satgutier@umich.edu/***************************************************************************** 210152Satgutier@umich.edu * McPAT/CACTI 310152Satgutier@umich.edu * SOFTWARE LICENSE AGREEMENT 410152Satgutier@umich.edu * Copyright 2012 Hewlett-Packard Development Company, L.P. 510234Syasuko.eckert@amd.com * Copyright (c) 2010-2013 Advanced Micro Devices, Inc. 610152Satgutier@umich.edu * All Rights Reserved 710152Satgutier@umich.edu * 810152Satgutier@umich.edu * Redistribution and use in source and binary forms, with or without 910152Satgutier@umich.edu * modification, are permitted provided that the following conditions are 1010152Satgutier@umich.edu * met: redistributions of source code must retain the above copyright 1110152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer; 1210152Satgutier@umich.edu * redistributions in binary form must reproduce the above copyright 1310152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer in the 1410152Satgutier@umich.edu * documentation and/or other materials provided with the distribution; 1510152Satgutier@umich.edu * neither the name of the copyright holders nor the names of its 1610152Satgutier@umich.edu * contributors may be used to endorse or promote products derived from 1710152Satgutier@umich.edu * this software without specific prior written permission. 1810152Satgutier@umich.edu 1910152Satgutier@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2010152Satgutier@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2110152Satgutier@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2210152Satgutier@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2310152Satgutier@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2410152Satgutier@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2510152Satgutier@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2610152Satgutier@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2710152Satgutier@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2810152Satgutier@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2910234Syasuko.eckert@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3010152Satgutier@umich.edu * 3110152Satgutier@umich.edu ***************************************************************************/ 3210152Satgutier@umich.edu 3310152Satgutier@umich.edu 3410152Satgutier@umich.edu 3510152Satgutier@umich.edu#ifndef __PARAMETER_H__ 3610152Satgutier@umich.edu#define __PARAMETER_H__ 3710152Satgutier@umich.edu 3810152Satgutier@umich.edu#include "area.h" 3910152Satgutier@umich.edu#include "cacti_interface.h" 4010152Satgutier@umich.edu#include "const.h" 4110152Satgutier@umich.edu#include "io.h" 4210152Satgutier@umich.edu 4310152Satgutier@umich.edu// parameters which are functions of certain device technology 4410234Syasuko.eckert@amd.comclass TechnologyParameter { 4510234Syasuko.eckert@amd.compublic: 4610234Syasuko.eckert@amd.com class DeviceType { 4710234Syasuko.eckert@amd.com public: 4810234Syasuko.eckert@amd.com double C_g_ideal; 4910234Syasuko.eckert@amd.com double C_fringe; 5010234Syasuko.eckert@amd.com double C_overlap; 5110234Syasuko.eckert@amd.com double C_junc; // C_junc_area 5210234Syasuko.eckert@amd.com double C_junc_sidewall; 5310234Syasuko.eckert@amd.com double l_phy; 5410234Syasuko.eckert@amd.com double l_elec; 5510234Syasuko.eckert@amd.com double R_nch_on; 5610234Syasuko.eckert@amd.com double R_pch_on; 5710234Syasuko.eckert@amd.com double Vdd; 5810234Syasuko.eckert@amd.com double Vth; 5910234Syasuko.eckert@amd.com double I_on_n; 6010234Syasuko.eckert@amd.com double I_on_p; 6110234Syasuko.eckert@amd.com double I_off_n; 6210234Syasuko.eckert@amd.com double I_off_p; 6310234Syasuko.eckert@amd.com double I_g_on_n; 6410234Syasuko.eckert@amd.com double I_g_on_p; 6510234Syasuko.eckert@amd.com double C_ox; 6610234Syasuko.eckert@amd.com double t_ox; 6710234Syasuko.eckert@amd.com double n_to_p_eff_curr_drv_ratio; 6810234Syasuko.eckert@amd.com double long_channel_leakage_reduction; 6910152Satgutier@umich.edu 7010234Syasuko.eckert@amd.com DeviceType(): C_g_ideal(0), C_fringe(0), C_overlap(0), C_junc(0), 7110234Syasuko.eckert@amd.com C_junc_sidewall(0), l_phy(0), l_elec(0), R_nch_on(0), R_pch_on(0), 7210234Syasuko.eckert@amd.com Vdd(0), Vth(0), 7310234Syasuko.eckert@amd.com I_on_n(0), I_on_p(0), I_off_n(0), I_off_p(0), I_g_on_n(0), 7410234Syasuko.eckert@amd.com I_g_on_p(0), 7510234Syasuko.eckert@amd.com C_ox(0), t_ox(0), n_to_p_eff_curr_drv_ratio(0), 7610234Syasuko.eckert@amd.com long_channel_leakage_reduction(0) { }; 7710234Syasuko.eckert@amd.com void reset() { 7810234Syasuko.eckert@amd.com C_g_ideal = 0; 7910234Syasuko.eckert@amd.com C_fringe = 0; 8010234Syasuko.eckert@amd.com C_overlap = 0; 8110234Syasuko.eckert@amd.com C_junc = 0; 8210234Syasuko.eckert@amd.com l_phy = 0; 8310234Syasuko.eckert@amd.com l_elec = 0; 8410234Syasuko.eckert@amd.com R_nch_on = 0; 8510234Syasuko.eckert@amd.com R_pch_on = 0; 8610234Syasuko.eckert@amd.com Vdd = 0; 8710234Syasuko.eckert@amd.com Vth = 0; 8810234Syasuko.eckert@amd.com I_on_n = 0; 8910234Syasuko.eckert@amd.com I_on_p = 0; 9010234Syasuko.eckert@amd.com I_off_n = 0; 9110234Syasuko.eckert@amd.com I_off_p = 0; 9210234Syasuko.eckert@amd.com I_g_on_n = 0; 9310234Syasuko.eckert@amd.com I_g_on_p = 0; 9410234Syasuko.eckert@amd.com C_ox = 0; 9510234Syasuko.eckert@amd.com t_ox = 0; 9610234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio = 0; 9710234Syasuko.eckert@amd.com long_channel_leakage_reduction = 0; 9810234Syasuko.eckert@amd.com } 9910234Syasuko.eckert@amd.com 10010234Syasuko.eckert@amd.com void display(uint32_t indent = 0); 10110234Syasuko.eckert@amd.com }; 10210234Syasuko.eckert@amd.com class InterconnectType { 10310234Syasuko.eckert@amd.com public: 10410234Syasuko.eckert@amd.com double pitch; 10510234Syasuko.eckert@amd.com double R_per_um; 10610234Syasuko.eckert@amd.com double C_per_um; 10710234Syasuko.eckert@amd.com double horiz_dielectric_constant; 10810234Syasuko.eckert@amd.com double vert_dielectric_constant; 10910234Syasuko.eckert@amd.com double aspect_ratio; 11010234Syasuko.eckert@amd.com double miller_value; 11110234Syasuko.eckert@amd.com double ild_thickness; 11210234Syasuko.eckert@amd.com 11310234Syasuko.eckert@amd.com InterconnectType(): pitch(0), R_per_um(0), C_per_um(0) { }; 11410234Syasuko.eckert@amd.com 11510234Syasuko.eckert@amd.com void reset() { 11610234Syasuko.eckert@amd.com pitch = 0; 11710234Syasuko.eckert@amd.com R_per_um = 0; 11810234Syasuko.eckert@amd.com C_per_um = 0; 11910234Syasuko.eckert@amd.com horiz_dielectric_constant = 0; 12010234Syasuko.eckert@amd.com vert_dielectric_constant = 0; 12110234Syasuko.eckert@amd.com aspect_ratio = 0; 12210234Syasuko.eckert@amd.com miller_value = 0; 12310234Syasuko.eckert@amd.com ild_thickness = 0; 12410234Syasuko.eckert@amd.com } 12510234Syasuko.eckert@amd.com 12610234Syasuko.eckert@amd.com void display(uint32_t indent = 0); 12710234Syasuko.eckert@amd.com }; 12810234Syasuko.eckert@amd.com class MemoryType { 12910234Syasuko.eckert@amd.com public: 13010234Syasuko.eckert@amd.com double b_w; 13110234Syasuko.eckert@amd.com double b_h; 13210234Syasuko.eckert@amd.com double cell_a_w; 13310234Syasuko.eckert@amd.com double cell_pmos_w; 13410234Syasuko.eckert@amd.com double cell_nmos_w; 13510234Syasuko.eckert@amd.com double Vbitpre; 13610234Syasuko.eckert@amd.com 13710234Syasuko.eckert@amd.com void reset() { 13810234Syasuko.eckert@amd.com b_w = 0; 13910234Syasuko.eckert@amd.com b_h = 0; 14010234Syasuko.eckert@amd.com cell_a_w = 0; 14110234Syasuko.eckert@amd.com cell_pmos_w = 0; 14210234Syasuko.eckert@amd.com cell_nmos_w = 0; 14310234Syasuko.eckert@amd.com Vbitpre = 0; 14410234Syasuko.eckert@amd.com } 14510234Syasuko.eckert@amd.com 14610234Syasuko.eckert@amd.com void display(uint32_t indent = 0); 14710234Syasuko.eckert@amd.com }; 14810234Syasuko.eckert@amd.com 14910234Syasuko.eckert@amd.com class ScalingFactor { 15010234Syasuko.eckert@amd.com public: 15110234Syasuko.eckert@amd.com double logic_scaling_co_eff; 15210234Syasuko.eckert@amd.com double core_tx_density; 15310234Syasuko.eckert@amd.com double long_channel_leakage_reduction; 15410234Syasuko.eckert@amd.com 15510234Syasuko.eckert@amd.com ScalingFactor(): logic_scaling_co_eff(0), core_tx_density(0), 15610234Syasuko.eckert@amd.com long_channel_leakage_reduction(0) { }; 15710234Syasuko.eckert@amd.com 15810234Syasuko.eckert@amd.com void reset() { 15910234Syasuko.eckert@amd.com logic_scaling_co_eff = 0; 16010234Syasuko.eckert@amd.com core_tx_density = 0; 16110234Syasuko.eckert@amd.com long_channel_leakage_reduction = 0; 16210234Syasuko.eckert@amd.com } 16310234Syasuko.eckert@amd.com 16410234Syasuko.eckert@amd.com void display(uint32_t indent = 0); 16510234Syasuko.eckert@amd.com }; 16610234Syasuko.eckert@amd.com 16710234Syasuko.eckert@amd.com double ram_wl_stitching_overhead_; 16810234Syasuko.eckert@amd.com double min_w_nmos_; 16910234Syasuko.eckert@amd.com double max_w_nmos_; 17010234Syasuko.eckert@amd.com double max_w_nmos_dec; 17110234Syasuko.eckert@amd.com double unit_len_wire_del; 17210234Syasuko.eckert@amd.com double FO4; 17310234Syasuko.eckert@amd.com double kinv; 17410234Syasuko.eckert@amd.com double vpp; 17510234Syasuko.eckert@amd.com double w_sense_en; 17610234Syasuko.eckert@amd.com double w_sense_n; 17710234Syasuko.eckert@amd.com double w_sense_p; 17810234Syasuko.eckert@amd.com double sense_delay; 17910234Syasuko.eckert@amd.com double sense_dy_power; 18010234Syasuko.eckert@amd.com double w_iso; 18110234Syasuko.eckert@amd.com double w_poly_contact; 18210234Syasuko.eckert@amd.com double spacing_poly_to_poly; 18310234Syasuko.eckert@amd.com double spacing_poly_to_contact; 18410234Syasuko.eckert@amd.com 18510234Syasuko.eckert@amd.com double w_comp_inv_p1; 18610234Syasuko.eckert@amd.com double w_comp_inv_p2; 18710234Syasuko.eckert@amd.com double w_comp_inv_p3; 18810234Syasuko.eckert@amd.com double w_comp_inv_n1; 18910234Syasuko.eckert@amd.com double w_comp_inv_n2; 19010234Syasuko.eckert@amd.com double w_comp_inv_n3; 19110234Syasuko.eckert@amd.com double w_eval_inv_p; 19210234Syasuko.eckert@amd.com double w_eval_inv_n; 19310234Syasuko.eckert@amd.com double w_comp_n; 19410234Syasuko.eckert@amd.com double w_comp_p; 19510234Syasuko.eckert@amd.com 19610234Syasuko.eckert@amd.com double dram_cell_I_on; 19710234Syasuko.eckert@amd.com double dram_cell_Vdd; 19810234Syasuko.eckert@amd.com double dram_cell_I_off_worst_case_len_temp; 19910234Syasuko.eckert@amd.com double dram_cell_C; 20010234Syasuko.eckert@amd.com double gm_sense_amp_latch; 20110234Syasuko.eckert@amd.com 20210234Syasuko.eckert@amd.com double w_nmos_b_mux; 20310234Syasuko.eckert@amd.com double w_nmos_sa_mux; 20410234Syasuko.eckert@amd.com double w_pmos_bl_precharge; 20510234Syasuko.eckert@amd.com double w_pmos_bl_eq; 20610234Syasuko.eckert@amd.com double MIN_GAP_BET_P_AND_N_DIFFS; 20710234Syasuko.eckert@amd.com double MIN_GAP_BET_SAME_TYPE_DIFFS; 20810234Syasuko.eckert@amd.com double HPOWERRAIL; 20910234Syasuko.eckert@amd.com double cell_h_def; 21010234Syasuko.eckert@amd.com 21110234Syasuko.eckert@amd.com double chip_layout_overhead; 21210234Syasuko.eckert@amd.com double macro_layout_overhead; 21310234Syasuko.eckert@amd.com double sckt_co_eff; 21410234Syasuko.eckert@amd.com 21510234Syasuko.eckert@amd.com double fringe_cap; 21610234Syasuko.eckert@amd.com 21710234Syasuko.eckert@amd.com uint64_t h_dec; 21810234Syasuko.eckert@amd.com 21910234Syasuko.eckert@amd.com DeviceType sram_cell; // SRAM cell transistor 22010234Syasuko.eckert@amd.com DeviceType dram_acc; // DRAM access transistor 22110234Syasuko.eckert@amd.com DeviceType dram_wl; // DRAM wordline transistor 22210234Syasuko.eckert@amd.com DeviceType peri_global; // peripheral global 22310234Syasuko.eckert@amd.com DeviceType cam_cell; // SRAM cell transistor 22410234Syasuko.eckert@amd.com 22510234Syasuko.eckert@amd.com InterconnectType wire_local; 22610234Syasuko.eckert@amd.com InterconnectType wire_inside_mat; 22710234Syasuko.eckert@amd.com InterconnectType wire_outside_mat; 22810234Syasuko.eckert@amd.com 22910234Syasuko.eckert@amd.com ScalingFactor scaling_factor; 23010234Syasuko.eckert@amd.com 23110234Syasuko.eckert@amd.com MemoryType sram; 23210234Syasuko.eckert@amd.com MemoryType dram; 23310234Syasuko.eckert@amd.com MemoryType cam; 23410152Satgutier@umich.edu 23510152Satgutier@umich.edu void display(uint32_t indent = 0); 23610152Satgutier@umich.edu 23710234Syasuko.eckert@amd.com void reset() { 23810234Syasuko.eckert@amd.com dram_cell_Vdd = 0; 23910234Syasuko.eckert@amd.com dram_cell_I_on = 0; 24010234Syasuko.eckert@amd.com dram_cell_C = 0; 24110234Syasuko.eckert@amd.com vpp = 0; 24210152Satgutier@umich.edu 24310234Syasuko.eckert@amd.com sense_delay = 0; 24410234Syasuko.eckert@amd.com sense_dy_power = 0; 24510234Syasuko.eckert@amd.com fringe_cap = 0; 24610152Satgutier@umich.edu// horiz_dielectric_constant = 0; 24710152Satgutier@umich.edu// vert_dielectric_constant = 0; 24810152Satgutier@umich.edu// aspect_ratio = 0; 24910152Satgutier@umich.edu// miller_value = 0; 25010152Satgutier@umich.edu// ild_thickness = 0; 25110152Satgutier@umich.edu 25210234Syasuko.eckert@amd.com dram_cell_I_off_worst_case_len_temp = 0; 25310152Satgutier@umich.edu 25410234Syasuko.eckert@amd.com sram_cell.reset(); 25510234Syasuko.eckert@amd.com dram_acc.reset(); 25610234Syasuko.eckert@amd.com dram_wl.reset(); 25710234Syasuko.eckert@amd.com peri_global.reset(); 25810234Syasuko.eckert@amd.com cam_cell.reset(); 25910152Satgutier@umich.edu 26010234Syasuko.eckert@amd.com scaling_factor.reset(); 26110152Satgutier@umich.edu 26210234Syasuko.eckert@amd.com wire_local.reset(); 26310234Syasuko.eckert@amd.com wire_inside_mat.reset(); 26410234Syasuko.eckert@amd.com wire_outside_mat.reset(); 26510152Satgutier@umich.edu 26610234Syasuko.eckert@amd.com sram.reset(); 26710234Syasuko.eckert@amd.com dram.reset(); 26810234Syasuko.eckert@amd.com cam.reset(); 26910152Satgutier@umich.edu 27010234Syasuko.eckert@amd.com chip_layout_overhead = 0; 27110234Syasuko.eckert@amd.com macro_layout_overhead = 0; 27210234Syasuko.eckert@amd.com sckt_co_eff = 0; 27310234Syasuko.eckert@amd.com } 27410152Satgutier@umich.edu}; 27510152Satgutier@umich.edu 27610152Satgutier@umich.edu 27710152Satgutier@umich.edu 27810234Syasuko.eckert@amd.comclass DynamicParameter { 27910234Syasuko.eckert@amd.compublic: 28010152Satgutier@umich.edu bool is_tag; 28110152Satgutier@umich.edu bool pure_ram; 28210152Satgutier@umich.edu bool pure_cam; 28310152Satgutier@umich.edu bool fully_assoc; 28410152Satgutier@umich.edu int tagbits; 28510152Satgutier@umich.edu int num_subarrays; // only for leakage computation -- the number of subarrays per bank 28610152Satgutier@umich.edu int num_mats; // only for leakage computation -- the number of mats per bank 28710152Satgutier@umich.edu double Nspd; 28810152Satgutier@umich.edu int Ndwl; 28910152Satgutier@umich.edu int Ndbl; 29010152Satgutier@umich.edu int Ndcm; 29110152Satgutier@umich.edu int deg_bl_muxing; 29210152Satgutier@umich.edu int deg_senseamp_muxing_non_associativity; 29310152Satgutier@umich.edu int Ndsam_lev_1; 29410152Satgutier@umich.edu int Ndsam_lev_2; 29510152Satgutier@umich.edu int number_addr_bits_mat; // per port 29610152Satgutier@umich.edu int number_subbanks_decode; // per_port 29710152Satgutier@umich.edu int num_di_b_bank_per_port; 29810152Satgutier@umich.edu int num_do_b_bank_per_port; 29910152Satgutier@umich.edu int num_di_b_mat; 30010152Satgutier@umich.edu int num_do_b_mat; 30110152Satgutier@umich.edu int num_di_b_subbank; 30210152Satgutier@umich.edu int num_do_b_subbank; 30310152Satgutier@umich.edu 30410152Satgutier@umich.edu int num_si_b_mat; 30510152Satgutier@umich.edu int num_so_b_mat; 30610152Satgutier@umich.edu int num_si_b_subbank; 30710152Satgutier@umich.edu int num_so_b_subbank; 30810234Syasuko.eckert@amd.com int num_si_b_bank_per_port; 30910234Syasuko.eckert@amd.com int num_so_b_bank_per_port; 31010152Satgutier@umich.edu 31110152Satgutier@umich.edu int number_way_select_signals_mat; 31210152Satgutier@umich.edu int num_act_mats_hor_dir; 31310152Satgutier@umich.edu 31410152Satgutier@umich.edu int num_act_mats_hor_dir_sl; 31510152Satgutier@umich.edu bool is_dram; 31610152Satgutier@umich.edu double V_b_sense; 31710152Satgutier@umich.edu unsigned int num_r_subarray; 31810152Satgutier@umich.edu unsigned int num_c_subarray; 31910152Satgutier@umich.edu int tag_num_r_subarray;//sheng: fully associative cache tag and data must be computed together, data and tag must be separate 32010152Satgutier@umich.edu int tag_num_c_subarray; 32110152Satgutier@umich.edu int data_num_r_subarray; 32210152Satgutier@umich.edu int data_num_c_subarray; 32310152Satgutier@umich.edu int num_mats_h_dir; 32410152Satgutier@umich.edu int num_mats_v_dir; 32510152Satgutier@umich.edu uint32_t ram_cell_tech_type; 32610152Satgutier@umich.edu double dram_refresh_period; 32710152Satgutier@umich.edu 32810152Satgutier@umich.edu DynamicParameter(); 32910152Satgutier@umich.edu DynamicParameter( 33010152Satgutier@umich.edu bool is_tag_, 33110152Satgutier@umich.edu int pure_ram_, 33210152Satgutier@umich.edu int pure_cam_, 33310152Satgutier@umich.edu double Nspd_, 33410152Satgutier@umich.edu unsigned int Ndwl_, 33510152Satgutier@umich.edu unsigned int Ndbl_, 33610152Satgutier@umich.edu unsigned int Ndcm_, 33710152Satgutier@umich.edu unsigned int Ndsam_lev_1_, 33810152Satgutier@umich.edu unsigned int Ndsam_lev_2_, 33910152Satgutier@umich.edu bool is_main_mem_); 34010152Satgutier@umich.edu 34110152Satgutier@umich.edu int use_inp_params; 34210152Satgutier@umich.edu unsigned int num_rw_ports; 34310152Satgutier@umich.edu unsigned int num_rd_ports; 34410152Satgutier@umich.edu unsigned int num_wr_ports; 34510152Satgutier@umich.edu unsigned int num_se_rd_ports; // number of single ended read ports 34610152Satgutier@umich.edu unsigned int num_search_ports; 34710152Satgutier@umich.edu unsigned int out_w;// == nr_bits_out 34810152Satgutier@umich.edu bool is_main_mem; 34910152Satgutier@umich.edu Area cell, cam_cell;//cell is the sram_cell in both nomal cache/ram and FA. 35010152Satgutier@umich.edu bool is_valid; 35110152Satgutier@umich.edu}; 35210152Satgutier@umich.edu 35310152Satgutier@umich.edu 35410152Satgutier@umich.edu 35510152Satgutier@umich.eduextern InputParameter * g_ip; 35610152Satgutier@umich.eduextern TechnologyParameter g_tp; 35710152Satgutier@umich.edu 35810152Satgutier@umich.edu#endif 35910152Satgutier@umich.edu 360