Searched refs:si (Results 1 - 23 of 23) sorted by relevance

/gem5/src/arch/generic/
H A Ddecode_cache.cc45 StaticInstPtr &si = decodePages.lookup(addr); local
46 if (si && (si->machInst == mach_inst))
47 return si;
51 si = iter->second;
52 return si;
55 si = decoder->decodeInst(mach_inst);
56 instMap[mach_inst] = si;
57 return si;
/gem5/src/cpu/
H A Dexec_context.hh89 virtual RegVal readIntRegOperand(const StaticInst *si, int idx) = 0;
92 virtual void setIntRegOperand(const StaticInst *si,
105 virtual RegVal readFloatRegOperandBits(const StaticInst *si, int idx) = 0;
109 virtual void setFloatRegOperandBits(const StaticInst *si,
118 readVecRegOperand(const StaticInst *si, int idx) const = 0;
122 getWritableVecRegOperand(const StaticInst *si, int idx) = 0;
126 setVecRegOperand(const StaticInst *si, int idx,
134 readVec8BitLaneOperand(const StaticInst *si, int idx) const = 0;
138 readVec16BitLaneOperand(const StaticInst *si, int idx) const = 0;
142 readVec32BitLaneOperand(const StaticInst *si, in
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H A Dinst_pb_trace.hh69 const StaticInstPtr si, TheISA::PCState pc,
71 : InstRecord(when, tc, si, pc, mi), tracer(_tracer)
92 StaticInstPtr si, TheISA::PCState pc, const
122 * @param si for the machInst and opClass
125 void traceInst(ThreadContext *tc, StaticInstPtr si, TheISA::PCState pc);
128 * @param si for the machInst and opClass
133 void traceMem(StaticInstPtr si, Addr a, Addr s, unsigned f);
68 InstPBTraceRecord(InstPBTrace& _tracer, Tick when, ThreadContext *tc, const StaticInstPtr si, TheISA::PCState pc, const StaticInstPtr mi = NULL) argument
H A Dinst_pb_trace.cc123 InstPBTrace::getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr si, argument
130 return new InstPBTraceRecord(*this, when, tc, si, pc, mi);
135 InstPBTrace::traceInst(ThreadContext *tc, StaticInstPtr si, TheISA::PCState pc) argument
144 size_t instSize = si->asBytes(buf.get(), bufSize);
148 instSize = si->asBytes(buf.get(), bufSize);
162 curMsg->set_type(static_cast<ProtoMessage::Inst_InstType>(si->opClass()));
166 InstPBTrace::traceMem(StaticInstPtr si, Addr a, Addr s, unsigned f) argument
171 curMsg->set_type(static_cast<ProtoMessage::Inst_InstType>(si->opClass()));
H A Dbase_dyn_inst.hh671 void setIntRegOperand(const StaticInst *si, int idx, RegVal val) argument
677 void setCCRegOperand(const StaticInst *si, int idx, RegVal val) argument
683 void setVecRegOperand(const StaticInst *si, int idx, argument
691 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) argument
697 void setVecElemOperand(const StaticInst *si, int idx, const VecElem val) argument
703 void setVecPredRegOperand(const StaticInst *si, int idx, argument
/gem5/src/cpu/simple/
H A Dexec_context.hh178 readIntRegOperand(const StaticInst *si, int idx) override
181 const RegId& reg = si->srcRegIdx(idx);
188 setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
191 const RegId& reg = si->destRegIdx(idx);
199 readFloatRegOperandBits(const StaticInst *si, int idx) override
202 const RegId& reg = si->srcRegIdx(idx);
210 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
213 const RegId& reg = si->destRegIdx(idx);
220 readVecRegOperand(const StaticInst *si, int idx) const override
223 const RegId& reg = si
254 readVecLaneOperand(const StaticInst *si, int idx) const argument
288 setVecLaneOperandT(const StaticInst *si, int idx, const LD& val) argument
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/gem5/src/cpu/o3/
H A Ddyn_inst.hh174 readMiscRegOperand(const StaticInst *si, int idx) override
176 const RegId& reg = si->srcRegIdx(idx);
185 setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
187 const RegId& reg = si->destRegIdx(idx);
271 readIntRegOperand(const StaticInst *si, int idx) override
277 readFloatRegOperandBits(const StaticInst *si, int idx) override
283 readVecRegOperand(const StaticInst *si, int idx) const override
292 getWritableVecRegOperand(const StaticInst *si, int idx) override
301 readVec8BitLaneOperand(const StaticInst *si, int idx) const override
308 readVec16BitLaneOperand(const StaticInst *si, in
330 setVecLaneOperandT(const StaticInst *si, int idx, const LD& val) argument
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/gem5/src/cpu/minor/
H A Dexec_context.hh144 readIntRegOperand(const StaticInst *si, int idx) override
146 const RegId& reg = si->srcRegIdx(idx);
152 readFloatRegOperandBits(const StaticInst *si, int idx) override
154 const RegId& reg = si->srcRegIdx(idx);
160 readVecRegOperand(const StaticInst *si, int idx) const override
162 const RegId& reg = si->srcRegIdx(idx);
168 getWritableVecRegOperand(const StaticInst *si, int idx) override
170 const RegId& reg = si->destRegIdx(idx);
176 readVecElemOperand(const StaticInst *si, int idx) const override
178 const RegId& reg = si
278 setVecLaneOperandT(const StaticInst *si, int idx, const LD& val) argument
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/gem5/src/cpu/checker/
H A Dcpu.hh192 readIntRegOperand(const StaticInst *si, int idx) override
194 const RegId& reg = si->srcRegIdx(idx);
200 readFloatRegOperandBits(const StaticInst *si, int idx) override
202 const RegId& reg = si->srcRegIdx(idx);
211 readVecRegOperand(const StaticInst *si, int idx) const override
213 const RegId& reg = si->srcRegIdx(idx);
222 getWritableVecRegOperand(const StaticInst *si, int idx) override
224 const RegId& reg = si->destRegIdx(idx);
233 readVec8BitLaneOperand(const StaticInst *si, int idx) const override
235 const RegId& reg = si
270 setVecLaneOperandT(const StaticInst *si, int idx, const LD& val) argument
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/gem5/src/arch/riscv/
H A Ddecoder.cc89 StaticInstPtr si = decodeInst(mach_inst); local
90 instMap[mach_inst] = si;
91 return si;
/gem5/src/sim/power/
H A Dmathexpr_powermodel.cc144 auto si = dynamic_cast<const ScalarInfo *>(info); local
145 if (si)
146 return si->value();
/gem5/src/arch/power/
H A Dtypes.hh55 Bitfield<15, 0> si; member in namespace:PowerISA
/gem5/src/arch/power/insts/
H A Dinteger.hh112 imm(sext<16>(machInst.si)),
113 uimm(machInst.si)
/gem5/src/arch/x86/
H A Ddecoder.cc65 if (instBytes->si) {
154 instBytes->si = NULL;
688 StaticInstPtr si = decodeInst(mach_inst);
689 (*instMap)[mach_inst] = si;
690 return si;
701 StaticInstPtr &si = instBytes->si; local
702 if (si)
703 return si;
733 si
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H A Dsystem.cc174 cs.si = numGDTEntries - 1;
186 ds.si = numGDTEntries - 1;
205 tss.si = numGDTEntries - 1;
H A Dprocess.cc268 csLowPL.si = numGDTEntries - 1;
282 dsLowPL.si = numGDTEntries - 1;
296 ds.si = numGDTEntries - 1;
310 cs.si = numGDTEntries - 1;
314 scall.si = csLowPL.si;
318 sret.si = dsLowPL.si;
343 tssSel.si = numGDTEntries - 1;
H A Ddecoder.hh74 StaticInstPtr si; member in struct:X86ISA::Decoder::InstBytes
/gem5/src/base/
H A Dcp_annotate.cc1147 SmStack::iterator si; local
1148 si = smStack.begin();
1151 while (si != smStack.end()) {
1152 paramOut(os, csprintf("smStackId%d.sys", x), si->first.first);
1153 paramOut(os, csprintf("smStackId%d.frame", x), si->first.second);
1154 paramOut(os, csprintf("smStackId%d.count", x), si->second.size());
1155 for (y = 0; y < si->second.size(); y++)
1156 paramOut(os, csprintf("smStackId%d_%d", x, y), si->second[y]);
1157 x++; si++;
H A Dcp_annotate.hh315 getSm(int sysi, std::string si, uint64_t id) argument
318 Id smid = Id(si, id);
/gem5/ext/mcpat/cacti/
H A Dwire.cc628 double sp, si; local
630 si = repeater_size;
637 for (i = si; i > 1; i--) {
639 if (j == sp && i == si) {
642 global.area.h = si;
/gem5/ext/pybind11/tests/
H A Dtest_methods_and_attributes.cpp421 .def("__str__", [](const StrIssue &si) {
422 return "StrIssue[" + std::to_string(si.val) + "]"; }
/gem5/src/arch/x86/regs/
H A Dmisc.hh862 Bitfield<15, 3> si; // Selector Index member in namespace:X86ISA
/gem5/src/cpu/kvm/
H A Dbase.cc1225 onKickSignal(int signo, siginfo_t *si, void *data) argument

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