Searched refs:setMiscRegNoEffect (Results 1 - 25 of 50) sorted by relevance

12

/gem5/src/arch/sparc/
H A Dutility.cc75 src->setMiscRegNoEffect(MISCREG_TL, i);
76 dest->setMiscRegNoEffect(MISCREG_TL, i);
78 dest->setMiscRegNoEffect(MISCREG_TT,
80 dest->setMiscRegNoEffect(MISCREG_TPC,
82 dest->setMiscRegNoEffect(MISCREG_TNPC,
84 dest->setMiscRegNoEffect(MISCREG_TSTATE,
89 dest->setMiscRegNoEffect(MISCREG_TL, tl);
90 src->setMiscRegNoEffect(MISCREG_TL, tl);
94 // dest->setMiscRegNoEffect(MISCREG_Y,
96 // dest->setMiscRegNoEffect(MISCREG_CC
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H A Dua2005.cc100 setMiscRegNoEffect(miscReg, val);;
111 setMiscRegNoEffect(miscReg, val);
126 setMiscRegNoEffect(miscReg, val);
140 setMiscRegNoEffect(miscReg, val);
144 setMiscRegNoEffect(miscReg, val);
152 setMiscRegNoEffect(miscReg, val);
161 setMiscRegNoEffect(miscReg, val & ULL(~0x7FFF));
166 setMiscRegNoEffect(miscReg, val);
174 setMiscRegNoEffect(miscReg, val);
182 setMiscRegNoEffect(miscRe
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H A Dfaults.cc332 tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
335 tc->setMiscRegNoEffect(MISCREG_TPC, pc.pc() & pcMask);
337 tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask);
340 tc->setMiscRegNoEffect(MISCREG_HTSTATE, hpstate);
343 tc->setMiscRegNoEffect(MISCREG_TT, tt);
352 tc->setMiscRegNoEffect(MISCREG_PSTATE, pstate);
358 tc->setMiscRegNoEffect(MISCREG_HPSTATE, hpstate);
397 tc->setMiscRegNoEffect(MISCREG_TL, TL);
415 tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
418 tc->setMiscRegNoEffect(MISCREG_TP
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H A Dprocess.cc120 tc->setMiscRegNoEffect(MISCREG_FSR, 0);
122 tc->setMiscRegNoEffect(MISCREG_TICK, 0);
129 // tc->setMiscRegNoEffect(MISCREG_OTHERWIN, 0);
132 // tc->setMiscRegNoEffect(MISCREG_CANRESTORE, 0);
135 // tc->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2);
138 // tc->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows);
143 // tc->setMiscRegNoEffect(MISCREG_WSTATE, 0);
146 tc->setMiscRegNoEffect(MISCREG_TL, 0);
157 tc->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15);
/gem5/src/arch/alpha/
H A Dutility.cc88 dest->setMiscRegNoEffect(MISCREG_FPCR,
90 dest->setMiscRegNoEffect(MISCREG_UNIQ,
92 dest->setMiscRegNoEffect(MISCREG_LOCKFLAG,
94 dest->setMiscRegNoEffect(MISCREG_LOCKADDR,
H A Dfaults.cc128 tc->setMiscRegNoEffect(IPR_EXC_ADDR, pc.pc());
132 tc->setMiscRegNoEffect(IPR_EXC_ADDR,
160 tc->setMiscRegNoEffect(IPR_VA, vaddr);
164 tc->setMiscRegNoEffect(IPR_MM_STAT,
170 tc->setMiscRegNoEffect(IPR_VA_FORM,
182 tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
183 tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
H A Disa.hh80 void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0);
H A Dprocess.cc190 tc->setMiscRegNoEffect(IPR_DTB_ASN, _pid << 57);
218 tc->setMiscRegNoEffect(IPR_ICM, mode_user << 3);
219 tc->setMiscRegNoEffect(IPR_DTB_CM, mode_user << 3);
221 tc->setMiscRegNoEffect(IPR_MCSR, 0);
H A Dev5.cc102 tc->setMiscRegNoEffect(i, 0);
105 tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
106 tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
107 tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
481 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
H A Dinterrupts.hh215 tc->setMiscRegNoEffect(IPR_ISR, newSummary);
216 tc->setMiscRegNoEffect(IPR_INTID, newIpl);
H A Disa.cc117 ISA::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
/gem5/src/arch/mips/
H A Dremote_gdb.cc194 context->setMiscRegNoEffect(MISCREG_STATUS, r.sr);
197 context->setMiscRegNoEffect(MISCREG_BADVADDR, r.badvaddr);
198 context->setMiscRegNoEffect(MISCREG_CAUSE, r.cause);
H A Disa.cc185 setMiscRegNoEffect(MISCREG_PRID, procId);
200 setMiscRegNoEffect(MISCREG_CONFIG, cfg);
222 setMiscRegNoEffect(MISCREG_CONFIG1, cfg1);
239 setMiscRegNoEffect(MISCREG_CONFIG2, cfg2);
255 setMiscRegNoEffect(MISCREG_CONFIG3, cfg3);
265 setMiscRegNoEffect(MISCREG_EBASE, eBase);
275 setMiscRegNoEffect(MISCREG_SRSCTL, scsCtl);
285 setMiscRegNoEffect(MISCREG_INTCTL, intCtl);
294 setMiscRegNoEffect(MISCREG_WATCHHI0, watchHi);
304 setMiscRegNoEffect(MISCREG_PERFCNT
448 ISA::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) function in class:MipsISA::ISA
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H A Dfaults.cc112 tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl);
117 tc->setMiscRegNoEffect(MISCREG_STATUS, status);
123 tc->setMiscRegNoEffect(MISCREG_EPC,
131 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
H A Dfaults.hh172 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
205 tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
240 tc->setMiscRegNoEffect(MISCREG_BADVADDR, this->vaddr);
245 tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
249 tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
H A Disa.hh98 void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0);
H A Dinterrupts.cc55 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
/gem5/src/arch/power/
H A Disa.hh79 setMiscRegNoEffect(int misc_reg, RegVal val) function in class:PowerISA::ISA
/gem5/src/arch/riscv/
H A Disa.hh79 void setMiscRegNoEffect(int misc_reg, RegVal val);
H A Disa.cc169 ISA::setMiscRegNoEffect(int misc_reg, RegVal val) function in class:RiscvISA::ISA
194 setMiscRegNoEffect(misc_reg, val);
/gem5/src/arch/x86/
H A Disa.hh70 void setMiscRegNoEffect(int miscReg, RegVal val);
H A Dprocess.cc586 tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
587 tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
588 tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
605 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
697 tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
698 tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
699 tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
700 tc->setMiscRegNoEffect(MISCREG_SEG_SEL(seg), 0xB);
701 tc->setMiscRegNoEffect(MISCREG_SEG_LIMIT(seg), (uint32_t)(-1));
718 tc->setMiscRegNoEffect(MISCREG_CS_ATT
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/gem5/src/arch/arm/
H A Dremote_gdb.cc234 context->setMiscRegNoEffect(MISCREG_CPSR, r.cpsr);
249 context->setMiscRegNoEffect(MISCREG_FPSR, r.fpsr);
250 context->setMiscRegNoEffect(MISCREG_FPCR, r.fpcr);
310 context->setMiscRegNoEffect(MISCREG_CPSR, r.cpsr);
/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc433 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
489 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
747 return isa->setMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1, val);
770 return isa->setMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1, val);
1070 isa->setMiscRegNoEffect(MISCREG_ICC_BPR0_EL1, val);
1072 isa->setMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_S, val);
1084 isa->setMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_NS, val);
1122 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1200 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL3, icc_ctlr_el3);
1222 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL
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/gem5/src/cpu/kvm/
H A Dx86_cpu.cc1031 #define APPLY_SREG(kreg, mreg) tc->setMiscRegNoEffect(mreg, sregs.kreg)
1058 tc->setMiscRegNoEffect(MISCREG_X87_TOP, top);
1059 tc->setMiscRegNoEffect(MISCREG_MXCSR, fpu.mxcsr);
1060 tc->setMiscRegNoEffect(MISCREG_FCW, fpu.fcw);
1061 tc->setMiscRegNoEffect(MISCREG_FSW, fpu.fsw);
1065 tc->setMiscRegNoEffect(MISCREG_FTW, ftw);
1066 tc->setMiscRegNoEffect(MISCREG_FTAG, ftw);
1068 tc->setMiscRegNoEffect(MISCREG_FOP, fpu.last_opcode);
1081 tc->setMiscRegNoEffect(MISCREG_FISEG, 0);
1082 tc->setMiscRegNoEffect(MISCREG_FIOF
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