dev/arm/gic_v3_cpu_interface.cc

433                       isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
489                       isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
747             return isa->setMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1, val);
770             return isa->setMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1, val);
1070                 isa->setMiscRegNoEffect(MISCREG_ICC_BPR0_EL1, val);
1072                 isa->setMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_S, val);
1084                 isa->setMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_NS, val);
1122           isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1200           isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL3, icc_ctlr_el3);
1222          isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1260               isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S, icc_ctlr_el1_s);
1261               isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS,
1318           isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1330           isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1, val);
1341           isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1364           isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1374           isa->setMiscRegNoEffect(
1376           isa->setMiscRegNoEffect(
1609     isa->setMiscRegNoEffect(misc_reg, val);
1626     isa->setMiscRegNoEffect(
1731         isa->setMiscRegNoEffect(apr_misc_reg, apr);
1755             isa->setMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i, vapr0);
1759             isa->setMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i, vapr1);
1836     isa->setMiscRegNoEffect(apr_idx, apr);
1872     isa->setMiscRegNoEffect(apr_idx, apr);
1875     isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el);
1910     isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el2);
2215     isa->setMiscRegNoEffect(MISCREG_ICH_HCR_EL2, ich_hcr_el2);