Searched refs:sel (Results 1 - 8 of 8) sorted by relevance
/gem5/src/dev/ |
H A D | intel_8254_timer.cc | 60 int sel = data.sel; local 62 if (sel == ReadBackCommand) 66 counter[sel]->latchCount(); 68 counter[sel]->setRW(data.rw); 69 counter[sel]->setMode(data.mode); 70 counter[sel]->setBCD(data.bcd);
|
H A D | intel_8254_timer.hh | 51 Bitfield<7, 6> sel; member in class:Intel8254Timer
|
/gem5/ext/dnet/ |
H A D | os.h | 75 # elif defined(sel) || defined(pyr) || defined(mc68000) || defined(sparc) || \
|
/gem5/src/base/ |
H A D | addr_range.hh | 84 * sel. The first (0) mask is used to get the LSB and the last for 85 * the MSB of sel. 89 /** The value to compare sel with. */ 103 * bits that are xored to determine one bit of the sel value, 105 * determines the least significant bit of sel, ...). If sel 116 * sel == _intlv_match 118 * sel[0] = a[8] ^ a[11] ^ a[13] 119 * sel[1] = a[15] ^ a[17] ^ a[19] 146 * sel 411 auto sel = 0; local [all...] |
/gem5/src/arch/arm/ |
H A D | pmu.cc | 260 "[PMSELR: 0x%x, PMSELER.sel: 0x%x, EVTYPER: 0x%x]\n", 261 reg_pmselr, reg_pmselr.sel, val); 262 setCounterTypeRegister(reg_pmselr.sel, val); 271 setCounterValue(reg_pmselr.sel, val); 369 return getCounterTypeRegister(reg_pmselr.sel); 379 return getCounterValue(reg_pmselr.sel) & 0xFFFFFFFF;
|
H A D | pmu.hh | 159 Bitfield<4, 0> sel; member in class:ArmISA::PMU
|
H A D | miscregs_types.hh | 620 Bitfield<4, 0> sel; member in namespace:ArmISA
|
H A D | isa.hh | 633 if (pmselr.sel == 31)
|
Completed in 13 milliseconds