Searched refs:sctlr (Results 1 - 8 of 8) sorted by relevance

/gem5/src/arch/arm/
H A Dtlb.cc582 if (sctlr.a || !(flags & AllowUnaligned)) {
694 if (sctlr.afe == 1 || te->longDescFormat)
708 (int)sctlr.rs);
709 if (!sctlr.xp) {
710 switch ((int)sctlr.rs) {
754 bool xn = te->xn || (isWritable && sctlr.wxn) ||
755 (ap == 3 && sctlr.uwxn && is_priv);
761 "priv:%d write:%d ns:%d sif:%d sctlr.afe: %d \n",
762 ap, is_priv, is_write, te->ns, scr.sif,sctlr.afe);
874 // sctlr
[all...]
H A Disa.cc227 SCTLR sctlr = 0; local
228 sctlr.te = (bool) sctlr_rst.te;
229 sctlr.nmfi = (bool) sctlr_rst.nmfi;
230 sctlr.v = (bool) sctlr_rst.v;
231 sctlr.u = 1;
232 sctlr.xp = 1;
233 sctlr.rao2 = 1;
234 sctlr.rao3 = 1;
235 sctlr.rao4 = 0xf; // SCTLR[6:3]
236 sctlr
[all...]
H A Dtable_walker.cc77 sctlr = 0;
134 sctlr(0), scr(0), cpsr(0), tcr(0),
269 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1);
274 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1);
279 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2);
284 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL3);
293 currState->sctlr = currState->tc->readMiscReg(snsBankedIndex(
301 sctlr = currState->sctlr;
459 assert(currState->sctlr
1024 memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, uint8_t texcb, bool s) argument
[all...]
H A Dfaults.cc314 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); local
315 if (sctlr.v) {
455 const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); local
456 span = !sctlr.span;
461 const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL2); local
462 span = !sctlr.span;
498 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); local
538 cpsr.t = sctlr.te;
539 cpsr.e = sctlr.ee;
544 cpsr.t = sctlr
[all...]
H A Dtable_walker.hh726 /** Cached copy of the sctlr as it existed when translation began */
727 SCTLR sctlr; member in class:ArmISA::TableWalker::LongDescriptor::WalkerState
841 /** Cached copy of the sctlr as it existed when translation began */
842 SCTLR sctlr; member in class:ArmISA::TableWalker::LongDescriptor
915 void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
H A Dtlb.hh414 SCTLR sctlr; member in class:ArmISA::TLB
H A Dmiscregs.cc1163 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); local
1164 if (el == EL0 && !sctlr.uma)
1170 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); local
1171 if (el == EL0 && !sctlr.dze)
1175 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); local
1176 if (el == EL0 && !sctlr.uci)
/gem5/src/arch/arm/insts/
H A Dstatic_inst.cc780 SCTLR sctlr = ((SCTLR)tc->readMiscReg(MISCREG_SCTLR_EL1));
786 trap = isWfe? !sctlr.ntwe : !sctlr.ntwi;

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