Searched refs:random (Results 1 - 25 of 50) sorted by relevance

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/gem5/src/cpu/testers/traffic_gen/
H A Dstream_gen.cc42 #include "base/random.hh"
50 case Enums::random:
61 // Pick a random entry in the vector of IDs
62 return svec[random_mt.random<size_t>(0, svec.size()-1)];
H A Drandom_gen.cc47 #include "base/random.hh"
63 (readPercent == 100 || random_mt.random(0, 100) < readPercent);
69 Addr addr = random_mt.random(startAddr, endAddr - 1);
98 Tick wait = random_mt.random(minPeriod, maxPeriod);
H A Dlinear_gen.cc47 #include "base/random.hh"
64 (readPercent == 100 || random_mt.random(0, 100) < readPercent);
104 Tick wait = random_mt.random(minPeriod, maxPeriod);
H A Ddram_gen.cc47 #include "base/random.hh"
97 (readPercent == 100 || random_mt.random(0, 100) < readPercent);
103 // pick a random bank
105 random_mt.random<unsigned int>(0, nbrOfBanksUtil - 1);
107 // pick a random rank
109 random_mt.random<unsigned int>(0, nbrOfRanks - 1);
113 // bits updated for random traffic mode
156 // start by picking a random address in the range
157 addr = random_mt.random<Addr>(startAddr, endAddr - 1);
175 // pick a random colum
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/gem5/src/base/
H A Drandom.hh46 * Mersenne twister random number generator.
52 #include <random>
83 random() function in class:Random
92 random() function in class:Random
101 random(T min, T max) function in class:Random
/gem5/ext/pybind11/docs/
H A Dbenchmark.py1 import random
23 ret = random.randint(0, nclasses - 1)
24 params = [random.randint(0, nclasses - 1) for i in range(nargs)]
55 ret = random.randint(0, nclasses - 1)
56 params = [random.randint(0, nclasses - 1) for i in range(nargs)]
/gem5/src/systemc/tests/tlm/endian_conv/
H A Dtestall.py42 Testing space (select a transaction at random from the space):
43 - with and without byte-enables (generated at random for each data word
52 - address in initiator buffer uniform random
59 - one random breakdown with each segment containing between 1 and N-1
70 import random
101 # create a random transaction
102 bus_width = random.choice(bus_widths)
104 data_width = random.choice(data_widths)
106 if random.random() < 0.2
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/gem5/src/mem/cache/replacement_policies/
H A Dbip_rp.cc35 #include "base/random.hh"
50 if (random_mt.random<unsigned>(1, 100) <= btp) {
H A Drandom_rp.cc36 #include "base/random.hh"
72 // Choose one candidate at random
73 ReplaceableEntry* victim = candidates[random_mt.random<unsigned>(0,
H A Dbrrip_rp.cc37 #include "base/random.hh"
84 if (random_mt.random<unsigned>(1, 100) <= btp) {
/gem5/src/mem/ruby/network/
H A DMessageBuffer.py40 randomization = Param.Bool(False, "Insert random delays on message \
42 random delays if RubySystem \
H A DMessageBuffer.cc35 #include "base/random.hh"
142 time += random_mt.random(0, 3); // [0...3]
143 if (random_mt.random(0, 7) == 0) { // 1 in 8 chance
144 time += 100 + random_mt.random(1, 15); // 100 + [1...15]
166 // random delays are inserted if either RubySystem level randomization flag
/gem5/tests/test-progs/asmtest/src/riscv/env/v/
H A Dvm.c197 unsigned int random = ENTROPY; local
199 uintptr_t paddr = DRAM_BASE + ((random % (2 * (MAX_TEST_PAGES + 1) * PGSIZE)) & -4);
201 if (random & 1) // perform a no-op write
206 random = lfsr63(random);
212 unsigned int random = ENTROPY; local
258 random = 1 + (random % MAX_TEST_PAGES);
263 freelist_nodes[i].addr = DRAM_BASE + (MAX_TEST_PAGES + random)*PGSIZE;
265 random
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/gem5/src/cpu/testers/rubytest/
H A DCheck.cc32 #include "base/random.hh"
50 m_access_mode = RubyAccessMode(random_mt.random(0,
62 if (false && (random_mt.random(0, 0xf) == 0)) {
63 initiatePrefetch(); // Prefetch from random processor
66 if (m_tester_ptr->getCheckFlush() && (random_mt.random(0, 0xff) == 0)) {
67 initiateFlush(); // issue a Flush request from random processor
86 int index = random_mt.random(0, m_num_readers - 1);
95 if (random_mt.random(0, 0x7) != 0) {
101 (random_mt.random(0, 0x1)))) {
143 int index = random_mt.random(
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H A DCheckTable.cc33 #include "base/random.hh"
114 return m_check_vector[random_mt.random<unsigned>(0, m_check_vector.size() - 1)];
/gem5/util/tlm/examples/master_port/
H A Dtraffic_generator.cc35 #include "base/random.hh"
56 wait(sc_core::sc_time((double)rnd.random(1,100), sc_core::SC_NS));
62 if (rnd.random(0,1)) // Generate a write request?
66 dataBuffer = rnd.random(0,0xffff);
73 trans->set_address(rnd.random(0, (int)(memSize-1)));
/gem5/src/cpu/testers/memtest/
H A Dmemtest.cc47 #include "base/random.hh"
224 unsigned cmd = random_mt.random(0, 100);
225 uint8_t data = random_mt.random<uint8_t>();
226 bool uncacheable = random_mt.random(0, 100) < percentUncacheable;
227 unsigned base = random_mt.random(0, 1);
233 unsigned offset = random_mt.random<unsigned>(0, size - 1);
247 bool do_functional = (random_mt.random(0, 100) < percentFunctional) &&
/gem5/configs/example/
H A Dmemtest.py46 import random
101 parser.add_option("-r", "--random", action="store_true",
102 help="Generate a random tree topology")
136 if options.random:
139 tree_depth = random.randint(1, 4)
140 cachespec = [random.randint(1, 3) for i in range(tree_depth)]
141 testerspec = [random.randint(1, 3) for i in range(tree_depth + 1)]
145 print("Generated random tree -c", ':'.join(map(str, cachespec)),
H A Dmemcheck.py46 import random
92 # caches. The traffic generators switch between random address streams
104 parser.add_option("-r", "--random", action="store_true",
105 help="Generate a random tree topology")
119 if options.random:
121 tree_depth = random.randint(1, 4)
122 cachespec = [random.randint(1, 3) for i in range(tree_depth)]
123 testerspec = [random.randint(1, 3) for i in range(tree_depth + 1)]
124 print("Generated random tree -c", ':'.join(map(str, cachespec)),
203 # Three states, with random, linea
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/gem5/src/cpu/testers/directedtest/
H A DSeriesRequestGenerator.cc32 #include "base/random.hh"
66 bool do_write = (random_mt.random(0, 100) < m_percent_writes);
/gem5/src/cpu/testers/garnet_synthetic_traffic/
H A DGarnetSyntheticTraffic.cc40 #include "base/random.hh"
151 // - generate a random number between 0 and 10^precision
155 unsigned trySending = random_mt.random<unsigned>(0, (int) injRange);
200 destination = random_mt.random<unsigned>(0, num_destinations - 1);
289 injReqType = random_mt.random(0, 2);
/gem5/src/cpu/pred/
H A Dtage_sc_l.cc45 #include "base/random.hh"
58 return (random_mt.random<int>() & 7) == 0;
299 if ((taken == pred_taken) && ((random_mt.random<int>() & 31) != 0)) {
308 if ((random_mt.random<int>() & 127) < 32) {
312 (random_mt.random<int>() & 1));
436 int nrand = random_mt.random<int>() & 3;
H A Dtage.cc45 #include "base/random.hh"
73 int nrand = random_mt.random<int>() & 3;
H A Dltage.cc45 #include "base/random.hh"
116 int nrand = random_mt.random<int>() & 3;
/gem5/src/dev/arm/
H A Dsmmu_v3_caches.cc67 random(seed),
408 return random.random<size_t>(0, associativity-1);
410 return random.random<size_t>(0, associativity-2);
613 return random.random<size_t>(0, associativity-1);
793 return random.random<size_t>(0, associativity-1);
957 return random
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