Searched refs:miscRegs (Results 1 - 4 of 4) sorted by relevance

/gem5/util/cpt_upgraders/
H A Darm-contextidr-el2.py8 miscRegs = cpt.get(sec, 'miscRegs').split()
10 miscRegs[599:599] = [0xFC001]
11 cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in miscRegs))
/gem5/src/arch/arm/
H A Disa.cc71 miscRegs[MISCREG_SCTLR_RST] = 0;
132 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
133 memset(miscRegs, 0, sizeof(miscRegs));
144 miscRegs[MISCREG_SEV_MAILBOX] = 1;
147 miscRegs[MISCREG_TLBTR] = 1;
158 miscRegs[MISCREG_MVFR0] = mvfr0;
168 miscRegs[MISCREG_MVFR1] = mvfr1;
173 miscRegs[MISCREG_PRRR_NS] =
187 miscRegs[MISCREG_NMRR_N
[all...]
H A Disa.hh377 RegVal miscRegs[NumMiscRegs]; member in class:ArmISA::ISA
481 CPSR cpsr = miscRegs[MISCREG_CPSR];
546 CPSR cpsr = miscRegs[MISCREG_CPSR];
632 PMSELR pmselr = miscRegs[MISCREG_PMSELR];
646 inSecureState(miscRegs[MISCREG_SCR],
647 miscRegs[MISCREG_CPSR]);
651 !inSecureState(miscRegs[MISCREG_SCR],
652 miscRegs[MISCREG_CPSR]));
679 inSecureState(miscRegs[MISCREG_SCR],
680 miscRegs[MISCREG_CPS
[all...]
/gem5/src/arch/power/
H A Disa.hh54 RegVal miscRegs[NumMiscRegs]; member in class:PowerISA::ISA

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