arch/arm/isa.cc

71     miscRegs[MISCREG_SCTLR_RST] = 0;
132     SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
133     memset(miscRegs, 0, sizeof(miscRegs));
144     miscRegs[MISCREG_SEV_MAILBOX] = 1;
147     miscRegs[MISCREG_TLBTR] = 1;
158     miscRegs[MISCREG_MVFR0] = mvfr0;
168     miscRegs[MISCREG_MVFR1] = mvfr1;
173     miscRegs[MISCREG_PRRR_NS] =
187     miscRegs[MISCREG_NMRR_NS] =
221         miscRegs[MISCREG_MVBAR] = system->resetAddr();
224     miscRegs[MISCREG_CPSR] = cpsr;
238     miscRegs[MISCREG_SCTLR_NS] = sctlr;
239     miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
240     miscRegs[MISCREG_HCPTR] = 0;
242     miscRegs[MISCREG_CPACR] = 0;
244     miscRegs[MISCREG_FPSID] = p->fpsid;
247         TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
249         miscRegs[MISCREG_TTBCR_NS] = ttbcr;
251         miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
255         miscRegs[MISCREG_SCTLR_S] = sctlr;
256         miscRegs[MISCREG_SCR] = 0;
257         miscRegs[MISCREG_VBAR_S] = 0;
260         miscRegs[MISCREG_SCR] = 1;
277         miscRegs[MISCREG_RVBAR_EL3] = rvbar;
281         miscRegs[MISCREG_RVBAR_EL2] = rvbar;
285         miscRegs[MISCREG_RVBAR_EL1] = rvbar;
296     miscRegs[MISCREG_CPSR] = cpsr;
300     miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
302         miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
303         miscRegs[MISCREG_SCR_EL3]   = 0x00000030;  // RES1 fields
306         miscRegs[MISCREG_HSCTLR] = 0x30c50830;
309         miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
311         miscRegs[MISCREG_SCR_EL3] = 1;
319     miscRegs[MISCREG_MIDR] = p->midr;
320     miscRegs[MISCREG_MIDR_EL1] = p->midr;
321     miscRegs[MISCREG_VPIDR] = p->midr;
323     miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
324     miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
325     miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
326     miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
327     miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
328     miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
330     miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
331     miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
332     miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
333     miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
335     miscRegs[MISCREG_ID_ISAR5] = insertBits(
336         miscRegs[MISCREG_ID_ISAR5], 19, 4,
344     miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
345     miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
346     miscRegs[MISCREG_ID_AA64DFR0_EL1] =
350     miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
351     miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
352     miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
353     miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
354     miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
355     miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1;
357     miscRegs[MISCREG_ID_DFR0_EL1] =
360     miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
363     miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0;  // SVEver 0
365         miscRegs[MISCREG_ZCR_EL3] = sveVL - 1;
367         miscRegs[MISCREG_ZCR_EL2] = sveVL - 1;
369         miscRegs[MISCREG_ZCR_EL1] = sveVL - 1;
375     miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
376         miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
379     miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
380         miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
383     miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
384         miscRegs[MISCREG_ID_AA64PFR0_EL1], 35, 32,
387     miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
388         miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
391     miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
392         miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
395     miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
396         miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
399     miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
400         miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
403     miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
404         miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
437     auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
438                                           |(miscRegs[upper] << 32));
459         cpsr = miscRegs[misc_reg];
632             cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
649             return miscRegs[MISCREG_CPSR] & 0x1;
653             return miscRegs[MISCREG_CPSR] & 0xc;
657             return miscRegs[MISCREG_CPSR] & 0x400000;
763         miscRegs[lower] = bits(v, 31, 0);
764         miscRegs[upper] = bits(v, 63, 32);
768         miscRegs[lower] = v;
786         CPSR old_cpsr = miscRegs[MISCREG_CPSR];
799                 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
1066                 SCTLR sctlr = miscRegs[sctlr_idx];
1069                 miscRegs[sctlr_idx] = (RegVal)new_sctlr;
1873                 CPSR cpsr = miscRegs[MISCREG_CPSR];
1890                 CPSR cpsr = miscRegs[MISCREG_CPSR];
1898                 CPSR cpsr = miscRegs[MISCREG_CPSR];
1909                 CPSR cpsr = miscRegs[MISCREG_CPSR];
2132     CPSR cpsr = miscRegs[MISCREG_CPSR];
2138         len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL1]).len;
2142         len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len;
2148                 static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len));
2152         len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len;
2157                 static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len));