Searched refs:miscRegName (Results 1 - 13 of 13) sorted by relevance

/gem5/src/arch/arm/
H A Disa_device.cc65 miscRegName[misc_reg]);
71 warn("Returning zero for read from miscreg %s\n", miscRegName[misc_reg]);
H A Dpmu.cc197 miscRegName[unflattenMiscReg(misc_reg)], val);
295 panic("Unexpected PMU register: %i\n", miscRegName[misc_reg]);
299 miscRegName[misc_reg]);
307 miscRegName[unflattenMiscReg(misc_reg)], val);
393 panic("Unexpected PMU register: %i\n", miscRegName[misc_reg]);
397 miscRegName[misc_reg]);
H A Disa.cc441 miscRegName[misc_reg], val & reg.res0());
445 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
470 miscRegName[misc_reg]);
473 miscRegName[misc_reg]);
509 miscRegName[misc_reg], val);
820 miscRegName[misc_reg], val);
823 miscRegName[misc_reg], val);
854 miscRegName[misc_reg], newVal);
868 miscRegName[misc_reg], newVal);
891 miscRegName[misc_re
[all...]
H A Dmiscregs.hh1002 const char * const miscRegName[] = { member in namespace:ArmISA
1868 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
1869 "The miscRegName array and NUM_MISCREGS are inconsistent.");
/gem5/src/arch/power/
H A Dmiscregs.hh43 const char * const miscRegName[NUM_MISCREGS] = { member in namespace:PowerISA
/gem5/src/arch/arm/kvm/
H A Darm_cpu.cc479 inform("%s: 0x%x\n", miscRegName[ri->idx], value);
535 const char *name(miscRegName[idx]);
548 const char *name(idx != NUM_MISCREGS ? miscRegName[idx] : "-");
576 inform("VFP [%s]: %s", miscRegName[idx], getAndFormatOneReg(id));
676 miscRegName[reg]);
715 miscRegName[idx]);
818 miscRegName[reg]);
855 miscRegName[idx]);
H A Darmv8_cpu.cc193 miscRegName[idx], op0, op1, crn, crm, op2,
392 sysRegMap.emplace_back(reg, idx, miscRegName[idx],
/gem5/src/dev/arm/
H A Dgeneric_timer.cc357 miscRegName[reg]);
414 warn("Writing to unknown register: %s\n", miscRegName[reg]);
504 warn("Reading from unknown register: %s\n", miscRegName[reg]);
513 DPRINTF(Timer, "Setting %s := 0x%x\n", miscRegName[reg], val);
521 DPRINTF(Timer, "Reading %s as 0x%x\n", miscRegName[reg], value);
H A Dgic_v3_cpu_interface.cc725 misc_reg, miscRegName[misc_reg]);
729 miscRegName[misc_reg], value);
738 miscRegName[misc_reg], val);
1606 misc_reg, miscRegName[misc_reg]);
/gem5/src/cpu/minor/
H A Ddyn_inst.cc148 /* This is an ugly test because not all archs. have miscRegName */
150 os << 'm' << misc_reg << '(' << TheISA::miscRegName[misc_reg] << member in class:Minor::TheISA
/gem5/src/arch/sparc/
H A Dua2005.cc74 static string miscRegName[NumMiscRegs] = local
88 return miscRegName[index];
/gem5/src/arch/arm/tracers/
H A Dtarmac_record.cc197 regName = miscRegName[regRelIdx];
/gem5/src/arch/arm/insts/
H A Dstatic_inst.cc370 ccprintf(os, "%s", ArmISA::miscRegName[reg_idx]);

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