Searched refs:miscRegInfo (Results 1 - 5 of 5) sorted by relevance

/gem5/src/arch/arm/
H A Disa.hh372 miscRegInfo[reg]);
595 } else if (miscRegInfo[reg][MISCREG_MUTEX]) {
644 if (miscRegInfo[reg][MISCREG_BANKED]) {
662 if (miscRegInfo[reg][MISCREG_BANKED64]) {
684 lower += S && miscRegInfo[lower][MISCREG_BANKED_CHILD];
685 upper += S && miscRegInfo[upper][MISCREG_BANKED_CHILD];
H A Dmiscregs.cc997 canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
998 miscRegInfo[reg][MISCREG_USR_NS_RD];
1006 canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1007 miscRegInfo[reg][MISCREG_PRI_NS_RD];
1010 canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1011 miscRegInfo[reg][MISCREG_MON_NS1_RD];
1014 canRead = miscRegInfo[reg][MISCREG_HYP_RD];
1020 assert(!miscRegInfo[reg][MISCREG_BANKED]);
1033 canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1034 miscRegInfo[re
2844 bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below member in namespace:ArmISA
[all...]
H A Disa.cc467 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
468 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
817 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
818 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
H A Dmiscregs.hh983 extern std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS];
/gem5/src/arch/arm/kvm/
H A Darmv8_cpu.cc380 const auto &info(miscRegInfo[idx]);

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