Searched refs:isr (Results 1 - 6 of 6) sorted by relevance

/gem5/src/arch/arm/
H A Dinterrupts.hh194 CPSR isr = 0; // ARM ARM states ISR reg uses same bit possitions as CPSR local
197 isr.i = (useHcrMux & hcr.imo) ? (interrupts[INT_VIRT_IRQ] || hcr.vi)
199 isr.f = (useHcrMux & hcr.fmo) ? (interrupts[INT_VIRT_FIQ] || hcr.vf)
201 isr.a = (useHcrMux & hcr.amo) ? hcr.va : interrupts[INT_ABT];
202 return isr;
/gem5/src/dev/net/
H A Dns_gige.cc239 reg = regs.isr;
744 regs.isr |= interrupts;
774 "interrupt written to ISR: intr=%#x isr=%#x imr=%#x\n",
775 interrupts, regs.isr, regs.imr);
777 if ((regs.isr & regs.imr)) {
779 if ((regs.isr & regs.imr & ISR_NODELAY) == 0)
788 reading isr and servicing. just telling you in case you were thinking
797 if (regs.isr & regs.imr & ISR_SWI) {
800 if (regs.isr & regs.imr & ISR_RXIDLE) {
803 if (regs.isr
[all...]
H A Dns_gige.hh69 uint32_t isr; member in struct:dp_regs
/gem5/system/alpha/h/
H A Dev5_defs.h105 #define isr 256 macro
/gem5/system/alpha/palcode/
H A Dplatform.S1338 mfpr r25, isr
1659 mfpr r4, isr
1781 mfpr r4, isr // mchk_interrupt pin asserted
H A Dosfpal.S1878 SAVE_IPR(isr,CNS_Q_ISR,r1)

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