Searched refs:intEnabled (Results 1 - 3 of 3) sorted by relevance
| /gem5/util/cpt_upgraders/ |
| H A D | arm-gicv2-banked-regs.py | 46 intEnabled = cpt.get(sec, 'intEnabled' ).split()
52 b_intEnabled = intEnabled[0]
56 del intEnabled[0]
62 cpt.set(sec, 'intEnabled', ' '.join(intEnabled))
76 cpt.set(new_sec, 'intEnabled', b_intEnabled)
|
| /gem5/src/dev/arm/ |
| H A D | gic_v2.hh | 183 uint32_t intEnabled; member in struct:GicV2::BankedRegs
205 intEnabled(0), pendingInt(0), activeInt(0),
216 uint32_t intEnabled[INT_BITS_MAX-1]; member in class:GicV2
220 return getBankedRegs(ctx).intEnabled;
222 return intEnabled[ix - 1];
|
| H A D | gic_v2.cc | 77 intEnabled {}, pendingInt {}, activeInt {},
988 SERIALIZE_ARRAY(intEnabled, INT_BITS_MAX-1);
1018 SERIALIZE_SCALAR(intEnabled);
1032 UNSERIALIZE_ARRAY(intEnabled, INT_BITS_MAX-1);
1077 UNSERIALIZE_SCALAR(intEnabled);
|
Completed in 9 milliseconds