Searched refs:if_name (Results 1 - 25 of 102) sorted by relevance

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/gem5/src/dev/
H A Dio_device.cc67 PioDevice::getPort(const std::string &if_name, PortID idx) argument
69 if (if_name == "pio") {
72 return ClockedObject::getPort(if_name, idx);
/gem5/src/dev/x86/
H A Di8259.hh96 getPort(const std::string &if_name, PortID idx=InvalidPortID) override
98 if (if_name == "inputs")
100 else if (if_name == "output")
103 return BasicPioDevice::getPort(if_name, idx);
H A Di8254.hh74 getPort(const std::string &if_name, PortID idx=InvalidPortID) override
76 if (if_name == "int_pin")
79 return BasicPioDevice::getPort(if_name, idx);
H A Dcmos.hh86 getPort(const std::string &if_name, PortID idx=InvalidPortID) override
88 if (if_name == "int_pin")
91 return BasicPioDevice::getPort(if_name, idx);
H A Di8042.hh132 getPort(const std::string &if_name, PortID idx=InvalidPortID) override
134 if (if_name == "mouse_int_pin")
136 else if (if_name == "keyboard_int_pin")
139 return BasicPioDevice::getPort(if_name, idx);
/gem5/src/cpu/testers/directedtest/
H A DRubyDirectedTester.cc82 RubyDirectedTester::getPort(const std::string &if_name, PortID idx) argument
84 if (if_name != "cpuPort") {
86 return ClockedObject::getPort(if_name, idx);
/gem5/src/mem/
H A Dexternal_master.cc64 ExternalMaster::getPort(const std::string &if_name, PortID idx) argument
66 if (if_name == "port") {
86 return SimObject::getPort(if_name, idx);
H A Daddr_mapper.cc57 AddrMapper::getPort(const std::string &if_name, PortID idx) argument
59 if (if_name == "master") {
61 } else if (if_name == "slave") {
64 return SimObject::getPort(if_name, idx);
H A Dexternal_master.hh125 Port &getPort(const std::string &if_name,
H A Dmem_delay.cc64 MemDelay::getPort(const std::string &if_name, PortID idx) argument
66 if (if_name == "master") {
68 } else if (if_name == "slave") {
71 return ClockedObject::getPort(if_name, idx);
H A Dexternal_slave.hh131 Port &getPort(const std::string &if_name,
H A Dmem_checker_monitor.cc77 MemCheckerMonitor::getPort(const std::string &if_name, PortID idx) argument
79 if (if_name == "master" || if_name == "mem_side") {
81 } else if (if_name == "slave" || if_name == "cpu_side") {
84 return SimObject::getPort(if_name, idx);
H A Dexternal_slave.cc197 ExternalSlave::getPort(const std::string &if_name, PortID idx) argument
199 if (if_name == "port") {
219 return SimObject::getPort(if_name, idx);
H A Dsimple_mem.cc245 SimpleMemory::getPort(const std::string &if_name, PortID idx) argument
247 if (if_name != "port") {
248 return AbstractMemory::getPort(if_name, idx);
H A Ddramsim2.hh194 Port &getPort(const std::string &if_name,
/gem5/src/learning_gem5/part2/
H A Dsimple_memobj.cc45 SimpleMemobj::getPort(const std::string &if_name, PortID idx) argument
50 if (if_name == "mem_side") {
52 } else if (if_name == "inst_port") {
54 } else if (if_name == "data_port") {
58 return SimObject::getPort(if_name, idx);
/gem5/src/dev/net/
H A Detherbus.hh74 Port &getPort(const std::string &if_name,
H A Ddist_etherlink.cc112 DistEtherLink::getPort(const std::string &if_name, PortID idx) argument
114 if (if_name == "int0")
116 return SimObject::getPort(if_name, idx);
H A Detherbus.cc85 EtherBus::getPort(const std::string &if_name, PortID idx) argument
H A Detherlink.cc92 EtherLink::getPort(const std::string &if_name, PortID idx) argument
94 if (if_name == "int0")
96 else if (if_name == "int1")
98 return SimObject::getPort(if_name, idx);
/gem5/src/systemc/core/
H A DSystemC.py66 def getPort(self, if_name, iex):
/gem5/src/cpu/testers/rubytest/
H A DRubyTester.cc132 RubyTester::getPort(const std::string &if_name, PortID idx) argument
134 if (if_name != "cpuInstPort" && if_name != "cpuInstDataPort" &&
135 if_name != "cpuDataPort") {
137 return ClockedObject::getPort(if_name, idx);
139 if (if_name == "cpuInstPort") {
148 } else if (if_name == "cpuInstDataPort") {
159 assert(if_name == "cpuDataPort");
/gem5/src/arch/x86/
H A Dinterrupts.hh222 Port &getPort(const std::string &if_name,
225 if (if_name == "int_master") {
227 } else if (if_name == "int_slave") {
230 return PioDevice::getPort(if_name, idx);
/gem5/src/sim/
H A Dsim_object.cc126 SimObject::getPort(const std::string &if_name, PortID idx) argument
128 fatal("%s does not have any port named %s\n", name(), if_name);
/gem5/src/mem/ruby/system/
H A DRubyPort.cc91 RubyPort::getPort(const std::string &if_name, PortID idx) argument
93 if (if_name == "mem_master_port") {
95 } else if (if_name == "pio_master_port") {
97 } else if (if_name == "mem_slave_port") {
99 } else if (if_name == "pio_slave_port") {
101 } else if (if_name == "master") {
109 } else if (if_name == "slave") {
120 return ClockedObject::getPort(if_name, idx);

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