| /gem5/src/mem/ruby/network/ |
| H A D | MessageBuffer.py | 41 enqueue times (enforced to have \
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| H A D | MessageBuffer.hh | 75 enqueue(m, current_time, delta);
102 void enqueue(MsgPtr message, Tick curTime, Tick delta);
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| H A D | MessageBuffer.cc | 90 // until schd cycle, but enqueue operations effect the visible
150 MessageBuffer::enqueue(MsgPtr message, Tick current_time, Tick delta) function in class:MessageBuffer
199 // compute the delay cycles and set enqueue time
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| /gem5/src/mem/ |
| H A D | dramsim2_wrapper.hh | 133 void enqueue(bool is_write, uint64_t addr);
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| H A D | dramsim2_wrapper.cc | 172 DRAMSim2Wrapper::enqueue(bool is_write, uint64_t addr) function in class:DRAMSim2Wrapper
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| H A D | dramsim2.cc | 231 wrapper.enqueue(pkt->isWrite(), pkt->getAddr());
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| /gem5/src/mem/ruby/structures/ |
| H A D | WireBuffer.hh | 75 void enqueue(MsgPtr message, Tick current_time, Tick delta);
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| H A D | WireBuffer.cc | 73 WireBuffer::enqueue(MsgPtr message, Tick current_time, Tick delta) function in class:WireBuffer
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| /gem5/src/mem/ruby/system/ |
| H A D | VIPERCoalescer.cc | 131 // enqueue Retry
225 m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency);
256 m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency);
284 m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency);
300 m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency);
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| H A D | DMASequencer.cc | 114 m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1)));
164 m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1)));
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| H A D | Sequencer.cc | 654 m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency);
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| H A D | GPUCoalescer.cc | 956 m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency);
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| /gem5/src/dev/net/ |
| H A D | etherswitch.cc | 150 it->enqueue(packet, interfaceId);
156 receiver->enqueue(packet, interfaceId);
166 EtherSwitch::Interface::enqueue(EthPacketPtr packet, unsigned senderId) function in class:EtherSwitch::Interface
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| H A D | etherswitch.hh | 83 * enqueue packet to the outputFifo
85 void enqueue(EthPacketPtr packet, unsigned senderId);
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| /gem5/src/mem/ruby/network/simple/ |
| H A D | Throttle.cc | 121 out->enqueue(msg_ptr, current_time,
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| H A D | PerfectSwitch.cc | 249 // enqueue func will modify the message
278 m_out[outgoing][vnet]->enqueue(msg_ptr, current_time,
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| /gem5/src/mem/ruby/network/garnet2.0/ |
| H A D | NetworkInterface.cc | 136 // is now space to enqueue a stalled message. However, we cannot wake
216 // If a tail flit is received, enqueue into the protocol buffers if
222 outNode_ptr[vnet]->enqueue(t_flit->get_msg_ptr(), curTime,
264 // It is possible to enqueue multiple outgoing credit flits if a message
294 outNode_ptr[vnet]->enqueue(stallFlit->get_msg_ptr(), curTime,
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| /gem5/src/mem/ruby/slicc_interface/ |
| H A D | AbstractController.cc | 355 getMemoryQueue()->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1)));
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