18191SN/A/* 28191SN/A * Copyright (c) 2010 Advanced Micro Devices, Inc. 38191SN/A * All rights reserved. 48191SN/A * 58191SN/A * Redistribution and use in source and binary forms, with or without 68191SN/A * modification, are permitted provided that the following conditions are 78191SN/A * met: redistributions of source code must retain the above copyright 88191SN/A * notice, this list of conditions and the following disclaimer; 98191SN/A * redistributions in binary form must reproduce the above copyright 108191SN/A * notice, this list of conditions and the following disclaimer in the 118191SN/A * documentation and/or other materials provided with the distribution; 128191SN/A * neither the name of the copyright holders nor the names of its 138191SN/A * contributors may be used to endorse or promote products derived from 148191SN/A * this software without specific prior written permission. 158191SN/A * 168191SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 178191SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 188191SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 198191SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 208191SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 218191SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 228191SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 238191SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 248191SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 258191SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 268191SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 278191SN/A * 288191SN/A * Author: Lisa Hsu 298191SN/A * 308191SN/A */ 318191SN/A 3210441Snilay@cs.wisc.edu#ifndef __MEM_RUBY_STRUCTURES_WIREBUFFER_HH__ 3310441Snilay@cs.wisc.edu#define __MEM_RUBY_STRUCTURES_WIREBUFFER_HH__ 348191SN/A 358191SN/A#include <iostream> 368229SN/A#include <string> 378191SN/A#include <vector> 388191SN/A 399230SN/A#include "mem/ruby/common/Consumer.hh" 4010893Snilay@cs.wisc.edu#include "mem/ruby/slicc_interface/Message.hh" 418191SN/A#include "params/RubyWireBuffer.hh" 428191SN/A#include "sim/sim_object.hh" 438191SN/A 448191SN/A////////////////////////////////////////////////////////////////////////////// 458191SN/A// This object was written to literally mimic a Wire in Ruby, in the sense 468191SN/A// that there is no way for messages to get reordered en route on the WireBuffer. 478191SN/A// With Message Buffers, even if randomization is off and ordered is on, 488191SN/A// messages can arrive in different orders than they were sent because of 498191SN/A// network issues. This mimics a Wire, such that that is not possible. This can 508191SN/A// allow for messages between closely coupled controllers that are not actually 518191SN/A// separated by a network in real systems to simplify coherence. 528191SN/A///////////////////////////////////////////////////////////////////////////// 538191SN/A 5410301Snilay@cs.wisc.educlass Message; 558191SN/A 568191SN/Aclass WireBuffer : public SimObject 578191SN/A{ 588191SN/A public: 598191SN/A typedef RubyWireBufferParams Params; 608191SN/A WireBuffer(const Params *p); 618191SN/A void init(); 628191SN/A 638191SN/A ~WireBuffer(); 648191SN/A 658191SN/A void wakeup(); 668191SN/A 678191SN/A void setConsumer(Consumer* consumer_ptr) 688191SN/A { 698191SN/A m_consumer_ptr = consumer_ptr; 708191SN/A } 718191SN/A Consumer* getConsumer() { return m_consumer_ptr; }; 728191SN/A void setDescription(const std::string& name) { m_description = name; }; 738191SN/A std::string getDescription() { return m_description; }; 748191SN/A 7511116Santhony.gutierrez@amd.com void enqueue(MsgPtr message, Tick current_time, Tick delta); 7611116Santhony.gutierrez@amd.com void dequeue(Tick current_time); 778191SN/A const Message* peek(); 7811116Santhony.gutierrez@amd.com void recycle(Tick current_time, Tick recycle_latency); 7911116Santhony.gutierrez@amd.com bool isReady(Tick current_time); 8011116Santhony.gutierrez@amd.com // infinite queue length 8111116Santhony.gutierrez@amd.com bool areNSlotsAvailable(int n, Tick current_time) { return true; }; 828191SN/A 838191SN/A void print(std::ostream& out) const; 848191SN/A uint64_t m_msg_counter; 858191SN/A 868191SN/A private: 878191SN/A // Private copy constructor and assignment operator 888191SN/A WireBuffer (const WireBuffer& obj); 898191SN/A WireBuffer& operator=(const WireBuffer& obj); 908191SN/A 918191SN/A // data members 928191SN/A Consumer* m_consumer_ptr; // Consumer to signal a wakeup() 938191SN/A std::string m_description; 948191SN/A 958191SN/A // queues where memory requests live 9610893Snilay@cs.wisc.edu std::vector<MsgPtr> m_message_queue; 978191SN/A}; 988191SN/A 999554SN/Astd::ostream& operator<<(std::ostream& out, const WireBuffer& obj); 1009554SN/A 10110441Snilay@cs.wisc.edu#endif // __MEM_RUBY_STRUCTURES_WireBuffer_HH__ 102