Searched refs:cycles (Results 1 - 23 of 23) sorted by relevance

/gem5/src/base/
H A Dtypes.cc34 operator<<(std::ostream &out, const Cycles & cycles) argument
36 out << cycles.c;
H A Dtypes.hh70 * number of clock cycles.
73 * typedef, aiming to avoid unintentional mixing of cycles and ticks
110 /** In-place addition of cycles. */
133 friend std::ostream& operator<<(std::ostream &out, const Cycles & cycles);
/gem5/src/systemc/tests/systemc/tracing/wif_trace/pct1/
H A Dtx.cpp77 void sio_tx::mark (int cycles) argument
81 for (n=0; n<cycles; n++) {
H A Dtx.h65 void mark(int cycles);
/gem5/src/mem/
H A Dserial_link.cc149 Cycles cycles = delay; local
150 cycles += Cycles(divCeil(pkt->getSize() * 8, serial_link.num_lanes
152 Tick t = serial_link.clockEdge(cycles);
210 Cycles cycles = delay; local
211 cycles += Cycles(divCeil(pkt->getSize() * 8,
213 Tick t = serial_link.clockEdge(cycles);
298 Cycles cycles = Cycles(divCeil(pkt->getSize() * 8, local
300 Tick t = serial_link.clockEdge(cycles);
343 Cycles cycles = Cycles(divCeil(pkt->getSize() * 8, local
345 Tick t = serial_link.clockEdge(cycles);
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/gem5/util/m5/jni/
H A Dgem5Op.java50 public native void quiesceCycle(long cycles); argument
/gem5/src/cpu/kvm/
H A Dtimer.hh85 * number of cycles or instructions executed in the guest. If such
113 * Convert cycles executed on the host into Ticks executed in the
117 * @return Host cycles executed in VM converted to simulation ticks
119 Tick ticksFromHostCycles(uint64_t cycles) { argument
120 return cycles * hostFactor * hostFreq;
153 * Convert a time in simulator ticks to host cycles
156 * @return Simulation ticks converted into CPU cycles on the host
/gem5/src/sim/
H A Dclocked_object.hh100 // perform the calculations in terms of relative cycles to
168 * curTick() is on a clock edge, the number of cycles in the parameter is
170 * clock edge, the number of cycles in the parameter is added to the next
173 * @param cycles The number of cycles into the future
177 * curTick() + [0, clockPeriod()) + clockPeriod() * cycles
180 clockEdge(Cycles cycles=Cycles(0)) const
186 return tick + clockPeriod() * cycles;
235 * accessor functions to relate ticks to the cycles of the object.
H A Dpseudo_inst.hh70 void quiesceCycles(ThreadContext *tc, uint64_t cycles);
H A Dpseudo_inst.cc263 quiesceCycles(ThreadContext *tc, uint64_t cycles) argument
265 DPRINTF(PseudoInst, "PseudoInst::quiesceCycles(%i)\n", cycles);
266 tc->quiesceTick(tc->getCpuPtr()->clockEdge(Cycles(cycles)));
/gem5/src/dev/arm/
H A Dsmmu_v3_proc.cc126 SMMUProcess::doDelay(Yield &yield, Cycles cycles) argument
129 scheduleWakeup(smmu.clockEdge(cycles));
133 a.delay = cycles * smmu.clockPeriod();
H A Dsmmu_v3_proc.hh116 void doDelay(Yield &yield, Cycles cycles);
/gem5/ext/drampower/src/
H A DMemoryPowerModel.h118 // Total background energy of all active standby cycles
122 // Total background energy of all precharge standby cycles
126 // Total energy of idle cycles in the active mode
130 // Total energy of idle cycles in the precharge mode
228 double calcIoTermEnergy(int64_t cycles, double period, double power, int64_t numBits) const;
229 // Sum quantities (e.g., operations, energy, cycles) that are stored in a per bank basis returning the total amount.
240 double calcTivEnergy(int64_t cycles, double current) const;
H A DMemoryPowerModel.cc133 // How long a single burst takes, measured in command-clock cycles.
197 // Using the number of cycles that at least one bank is active here
252 // Idle energy in the active standby clock cycles
254 // Idle energy in the precharge standby clock cycles
256 // fast-exit active power-down cycles energy
258 // fast-exit precharged power-down cycles energy
260 // slow-exit active power-down cycles energy
262 // slow-exit precharged power-down cycles energy
265 // self-refresh cycles energy including a refresh per self-refresh entry
272 // background energy during active auto-refresh cycles i
600 calcIoTermEnergy(int64_t cycles, double period, double power, int64_t numBits) const argument
606 calcTivEnergy(int64_t cycles, double current) const argument
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/gem5/src/mem/ruby/system/
H A DSequencer.cc310 Sequencer::recordMissLatency(const Cycles cycles, const RubyRequestType type, argument
317 m_latencyHist.sample(cycles);
318 m_typeLatencyHist[type]->sample(cycles);
321 m_missLatencyHist.sample(cycles);
322 m_missTypeLatencyHist[type]->sample(cycles);
325 m_missMachLatencyHist[respondingMach]->sample(cycles);
326 m_missTypeMachLatencyHist[type][respondingMach]->sample(cycles);
346 m_hitLatencyHist.sample(cycles);
347 m_hitTypeLatencyHist[type]->sample(cycles);
350 m_hitMachLatencyHist[respondingMach]->sample(cycles);
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/gem5/include/gem5/
H A Dm5ops.h46 void m5_quiesce_cycle(uint64_t cycles);
/gem5/tests/test-progs/insttest/src/riscv/
H A Drv64i.cpp335 uint64_t cycles = 0;
336 asm("rdcycle %0" : "=r" (cycles));
337 cout << "Cycles: " << cycles << endl;
338 return cycles > 0;
/gem5/ext/dsent/model/optical/
H A DSWMRLink.cc183 // Figure out how many cycles the laser needs to be on
184 double cycles = getInputPort("In")->getTransitionInfo().getFrequencyMultiplier(); local
187 laser->getInputPort("LaserEnable")->setTransitionInfo(TransitionInfo(0.0, 1.0, cycles - 1.0));
H A DSWSRLink.cc243 // Figure out how many cycles the laser needs to be on
244 double cycles = getInputPort("In")->getTransitionInfo().getFrequencyMultiplier(); local
247 laser->getInputPort("LaserEnable")->setTransitionInfo(TransitionInfo(0.0, 1.0, cycles - 1.0));
/gem5/util/m5/
H A Dlua_gem5Op.c67 uint64_t cycles = lua_tointeger(L, 1); local
68 m5_quiesce_cycle(cycles);
/gem5/src/cpu/o3/
H A Dcpu.cc411 .desc("Total number of cycles that the CPU has spent unscheduled due "
417 .desc("Total number of cycles that CPU has spent quiesced or waiting "
721 Cycles cycles(curCycle() - lastRunningCycle);
723 if (cycles != 0)
724 --cycles;
725 quiesceCycles += cycles;
1708 Cycles cycles(curCycle() - lastRunningCycle);
1710 if (cycles > 1) {
1711 --cycles;
1712 idleCycles += cycles;
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/gem5/src/systemc/tests/systemc/misc/sim_tests/cycle_dw8051_demo/
H A Dcycle_model.cpp96 bool ALL_CYCLES; /* flag to execute all cycles */
1048 // number of clock cycles.
1084 int cycles = 0; local
1091 // wait 4 cycles
1113 cycles++;
1262 sc_assert(cycles==(stretch_cycles+1));
1263 cycle_count += cycles;
1264 cycles2execute-=cycles;
1626 /* wait additional cycles */
1639 /* wait additional cycles */
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/gem5/tests/test-progs/asmtest/src/riscv/isa/macros/scalar/
H A Dtest_macros.h21 # of bubble cycles.

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