/gem5/src/arch/arm/ |
H A D | utility.hh | 273 mcrMrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn, argument 277 (crm << 1) | 285 mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt, argument 289 crm = (iss >> 1) & 0xF; 297 mcrrMrrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex rt2, argument 301 (crm << 1) | 309 uint32_t crm, uint32_t op2, IntRegIndex rt) 312 (crm << 1) | 308 msrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, IntRegIndex rt) argument
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H A D | miscregs.cc | 55 decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) argument 63 switch (crm) { 75 switch (crm) { 87 switch (crm) { 97 switch (crm) { 111 switch (crm) { 124 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]", 125 crn, opc1, crm, opc2); 132 decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) argument 138 switch (crm) { 930 decodeCP15Reg64(unsigned crm, unsigned opc1) argument 1200 decodeAArch64SysReg(unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2) argument [all...] |
H A D | utility.cc | 465 uint32_t crm; local 480 mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2); 482 trapToHype |= hdcr.tpm && (crn == 9) && (crm >= 12); 484 ((crn == 9) && ((crm <= 2) || ((crm >= 5) && (crm <= 8)))) || 485 ((crn == 10) && ((crm <= 1) || (crm == 4) || (crm == 8))) || 486 ((crn == 11) && ((crm < 606 uint32_t crm; local 655 uint32_t crm; local [all...] |
H A D | miscregs.hh | 987 unsigned crm, unsigned opc2); 989 unsigned crn, unsigned crm, 996 unsigned crm, unsigned opc2); 999 MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1);
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/gem5/src/arch/arm/kvm/ |
H A D | armv8_cpu.cc | 187 const uint64_t crm(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_CRM)); 190 decodeAArch64SysReg(op0, op1, crn, crm, op2)); 192 inform(" %s (op0: %i, op1: %i, crn: %i, crm: %i, op2: %i): %s", 193 miscRegName[idx], op0, op1, crn, crm, op2, 377 const uint64_t crm(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_CRM)); 379 const MiscRegIndex idx(decodeAArch64SysReg(op0, op1, crn, crm, op2));
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H A D | arm_cpu.cc | 105 #define REG_CP32(cpnum, crn, opc1, crm, opc2) ( \ 110 ((crm) << KVM_REG_ARM_CRM_SHIFT) | \ 113 #define REG_CP64(cpnum, opc1, crm) ( \ 117 ((crm) << KVM_REG_ARM_CRM_SHIFT)) 386 const unsigned crm(REG_CRM(id)); 394 return decodeCP14Reg(crn, opc1, crm, opc2); 397 return decodeCP15Reg(crn, opc1, crm, opc2);
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