Searched refs:commit (Results 1 - 19 of 19) sorted by relevance

/gem5/ext/
H A Dgit-commit-msg72 # - parse the commit message as (textLine+ blankLine*)*
187 git hash-object -t commit --stdin
/gem5/src/cpu/pred/
H A Dindirect.hh55 virtual void commit(InstSeqNum seq_num, ThreadID tid,
H A Dsimple_indirect.hh50 void commit(InstSeqNum seq_num, ThreadID tid, void * indirect_history);
H A Dsimple_indirect.cc123 SimpleIndirectPredictor::commit(InstSeqNum seq_num, ThreadID tid,
H A Dbpred_unit.cc360 iPred->commit(done_sn, tid, predHist[tid].back().indirectHistory);
422 // The commit stage then checks the ROB update and sends a signal to
473 // Remember the correct direction for the update at commit.
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64mi/
H A Daccess.S23 # jalr to an illegal address should commit (hence should write rd).
32 # A load to an illegal address should not commit.
/gem5/src/cpu/o3/
H A Dcpu.cc110 commit(this, params),
173 commit.setActiveThreads(&activeThreads);
180 commit.setTimeBuffer(&timeBuffer);
185 commit.setFetchQueue(&fetchQueue);
191 commit.setIEWQueue(&iewQueue);
192 commit.setRenameQueue(&renameQueue);
194 commit.setIEWStage(&iew);
196 rename.setCommitStage(&commit);
298 commit.setRenameMap(commitRenameMap);
302 commit
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H A Dcommit.hh62 * DefaultCommit handles single threaded and SMT commit. Its width is
63 * specified by the parameters; each cycle it tries to commit that
65 * commit instructions from. Non- speculative instructions must reach
67 * reach the head, commit will broadcast the instruction's sequence
105 /** Overall commit status. Used to determine if the CPU can deschedule
124 /** Overall commit status. */
126 /** Next commit status, to be set at the end of the cycle. */
193 /** Initializes the draining of commit. */
211 /** Ticks the commit stage, which tries to commit instruction
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H A Dinst_queue.hh228 void commit(const InstSeqNum &inst, ThreadID tid = 0);
357 * once the IQ gets a signal from commit. While it's redundant to
437 /** Delay between commit stage and the IQ.
H A Drename.hh64 * freeing up registers upon commit. Rename handles blocking if the
157 /** Sets pointer to commit stage. Used only for initialization. */
165 /** Pointer to commit stage. Used only for initialization. */
337 /** Wire to get commit's output from backwards time buffer. */
417 bool commit; member in struct:DefaultRename::Stalls
437 /** Delay between commit and rename, in ticks. */
H A Dcpu.hh93 * FullO3CPU class, has each of the stages (fetch through commit)
463 /** Architectural register accessors. Looks up in the commit
482 /** Sets the commit PC state of a specific thread. */
485 /** Reads the commit PC state of a specific thread. */
488 /** Reads the commit PC of a specific thread. */
491 /** Reads the commit micro PC of a specific thread. */
571 /** The commit stage. */
572 typename CPUPolicy::Commit commit; member in class:FullO3CPU
586 /** The commit rename map. */
H A Dcommit_impl.hh57 #include "cpu/o3/commit.hh"
78 // This will get reset by commit if it was switched out at the
136 return cpu->name() + ".commit";
155 .desc("The number of squashed insts skipped by commit")
160 .desc("The number of times commit has been forced to stall to "
270 .desc("number cycles where commit BW limit reached")
682 DPRINTF(Commit,"[tid:%i] Still Squashing, cannot commit any"
691 commit();
701 // The ROB has more instructions it can commit. Its next status
708 " ROB and ready to commit\
815 DefaultCommit<Impl>::commit() function in class:DefaultCommit
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H A Dinst_queue_impl.hh972 InstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) function in class:InstructionQueue
1431 // dependencies as these instructions must be executed at commit.
H A Diew_impl.hh138 * an instruction execution completes and it is marked ready to commit.
269 .desc("cumulative count of insts sent to commit")
345 // Setup wire to read information from time buffer, from commit.
373 // Setup wire to write instructions to commit.
627 // being added to the queue to commit without being processed by
628 // writebackInsts prior to being sent to commit.
645 // Add finished instruction to queue to commit.
996 // commit stage can go ahead and execute them, and mark
1066 // so that commit can process them when they reach the
1067 // head of commit
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/gem5/src/cpu/o3/probe/
H A Delastic_trace.hh45 * in the fetch, rename, iew and commit stages of the O3CPU. It processes the
76 * instruction progresses through the commit stage, the timing as well as
141 * to commit.
198 * instruction reaches the commit stage, e.g. execute timestamp.
210 * and instruction is marked as ready to commit
229 * is processed for commit or retire, if it is chosen to be written to
271 /* Tick when instruction was marked ready and sent to commit stage. */
276 bool commit; member in struct:ElasticTrace::TraceInfo
324 * container implemented is sequential as dependencies obey commit
327 * information and written to the trace in commit orde
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H A Delastic_trace.cc325 // Add record to depTrace with commit parameter as false.
362 // executed and is picked up by the commit probe listener. But a
383 // Add record to depTrace with commit parameter as true.
394 InstExecInfo* exec_info_ptr, bool commit)
403 new_record->commit = commit;
441 if (head_inst->isLoad() && !commit) {
470 // picked up by the commit probe listener. But a request is not
479 // As stores have to commit in order a store is dependent on the last
502 (commit
393 addDepTraceRecord(const DynInstConstPtr& head_inst, InstExecInfo* exec_info_ptr, bool commit) argument
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/gem5/util/maint/
H A Dcreate_patches.sh69 2. Filter commit messages.
143 echo "Filtering commit messages..."
/gem5/src/cpu/minor/
H A Dexecute.hh101 /** Modify instruction trace times on commit */
176 /** The last commit was the end of a full instruction so an interrupt
277 * this is used for determining if a thread should only commit microops */
298 /** Try and commit instructions from the ends of the functional unit
300 * If only_commit_microops is true then only commit upto the
304 * branch is set to any branch raised during commit. */
305 void commit(ThreadID thread_id, bool only_commit_microops, bool discard,
H A Dexecute.cc363 DPRINTF(MinorMem, "Trying to commit error response: %s\n",
505 /* Leave it up to commit to handle the fault */
778 /* Generate MinorTrace's MinorInst lines. Do this at commit
882 /* Set the CP SeqNum to the numOps commit number */
905 panic("We should never hit the case where we try to commit from a "
922 * Execute::commit
926 * 'commit' (in this function), the access is presented to the
928 * Execute::commit will commit it.
959 DPRINTF(MinorExecute, "Can't commit dat
1023 Execute::commit(ThreadID thread_id, bool only_commit_microops, bool discard, function in class:Minor::Execute
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