Searched refs:clk_divider (Results 1 - 9 of 9) sorted by relevance

/gem5/src/sim/
H A DClockDomain.py81 clk_divider = Param.Unsigned(1, "Frequency divider") variable in class:DerivedClockDomain
H A Dclock_domain.cc198 clockDivider(p->clk_divider)
/gem5/src/arch/x86/
H A DX86LocalApic.py64 clk_domain=Parent.clk_domain, clk_divider=16)
/gem5/configs/ruby/
H A DMI_example.py124 # clk_divider value is a fix to pass regression.
127 clk_divider=3)
H A DMESI_Two_Level.py172 # clk_divider value is a fix to pass regression.
175 clk_divider = 3)
H A DMOESI_CMP_directory.py193 # clk_divider value is a fix to pass regression.
196 clk_divider=3)
H A DMOESI_hammer.py172 # clk_divider value is a fix to pass regression.
175 clk_divider=3)
H A DMOESI_CMP_token.py189 # clk_divider value is a fix to pass regression.
192 clk_divider=3)
H A DMESI_Three_Level.py200 # clk_divider value is a fix to pass regression.
202 clk_domain = ruby_system.clk_domain, clk_divider = 3)

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