Searched refs:cause (Results 1 - 22 of 22) sorted by relevance

/gem5/tests/configs/
H A Dcheckpoint.py78 cause = e.getCause()
79 if cause in _exit_limit:
82 elif cause in _exit_normal:
85 print("Test failed: Unknown exit cause: %s" % cause)
129 cause = e.getCause()
130 if cause in _exit_normal:
133 print("Test failed: Unknown exit cause: %s" % cause)
/gem5/src/sim/
H A Dsim_events.cc61 cause(_cause), code(c), repeat(r)
68 cause(_cause), code(c), repeat(r)
110 cause(_cause), code(c), repeat(r)
120 exitSimLoop(cause, 0);
135 SERIALIZE_SCALAR(cause);
145 UNSERIALIZE_SCALAR(cause);
154 : Event(Sim_Exit_Pri), cause(_cause), downCounter(counter)
168 exitSimLoop(cause, 0);
H A Dsim_events.hh58 std::string cause; member in class:GlobalSimLoopExitEvent
67 const std::string getCause() const { return cause; }
79 std::string cause; member in class:LocalSimLoopExitEvent
87 const std::string getCause() const { return cause; }
106 std::string cause; // string explaining why we're terminating member in class:CountedExitEvent
/gem5/src/arch/mips/
H A Dinterrupts.cc47 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); local
48 return cause.ip;
53 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); local
54 cause.ip = val;
55 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
123 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); local
124 if (status.im && cause.ip)
138 CauseReg M5_VAR_USED cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); local
140 (unsigned)status.im, (unsigned)cause.ip);
H A Dfaults.cc127 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); local
128 cause.excCode = excCode;
129 cause.bd = delay_slot ? 1 : 0;
130 cause.ce = 0;
131 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
H A Dremote_gdb.hh62 uint32_t cause; member in struct:MipsISA::RemoteGDB::MipsGdbRegCache::__anon4
H A Dremote_gdb.cc181 r.cause = context->readMiscRegNoEffect(MISCREG_CAUSE);
198 context->setMiscRegNoEffect(MISCREG_CAUSE, r.cause);
H A Dfaults.hh170 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); local
171 cause.ce = coProcID;
172 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
183 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); local
185 return cause.iv ? 0x200 : 0x180;
/gem5/util/systemc/systemc_within_gem5/systemc_simple_object/
H A Dconfig.py58 cause = m5.simulate(m5.MaxTick).getCause() variable
59 print(cause)
/gem5/configs/example/
H A Dsc_main.py44 cause = m5.simulate(m5.MaxTick).getCause() variable
/gem5/src/systemc/tests/
H A Dconfig.py47 cause = m5.simulate(m5.MaxTick).getCause() variable
H A Dverify.py360 def failed(self, test, cause, note=''):
362 self._failed.setdefault(cause, []).append(test)
375 cause: map(lambda t: t.props, tests) for
376 cause, tests in self._failed.iteritems()
392 for cause, tests in sorted(self._failed.items()):
393 block = ' ' + cause.capitalize() + ':\n'
/gem5/util/systemc/systemc_within_gem5/systemc_sc_main/
H A Dconfig.py64 cause = m5.simulate(m5.MaxTick).getCause() variable
/gem5/tests/test-progs/asmtest/src/riscv/env/v/
H A Dvm.c123 void handle_fault(uintptr_t addr, uintptr_t cause) argument
132 assert(!(user_l3pt[addr/PGSIZE] & PTE_D) && cause == CAUSE_STORE_PAGE_FAULT);
164 if (tf->cause == CAUSE_USER_ECALL)
173 else if (tf->cause == CAUSE_ILLEGAL_INSTRUCTION)
186 else if (tf->cause == CAUSE_FETCH_PAGE_FAULT || tf->cause == CAUSE_LOAD_PAGE_FAULT || tf->cause == CAUSE_STORE_PAGE_FAULT)
187 handle_fault(tf->badvaddr, tf->cause);
196 // cause coherence misses without affecting program semantics
H A Driscv_test.h67 long cause; member in struct:__anon74
H A Dentry.S114 # get sr, epc, badvaddr, cause
/gem5/src/arch/riscv/
H A Dfaults.cc85 MiscRegIndex cause, epc, tvec, tval; local
88 cause = MISCREG_UCAUSE;
97 cause = MISCREG_SCAUSE;
107 cause = MISCREG_MCAUSE;
121 // Set fault cause, privilege, and return PC
122 tc->setMiscReg(cause,
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64mi/
H A Dmcsr.S26 # Check that reading the following CSRs doesn't cause an exception
31 # Check that writing hte following CSRs doesn't cause an exception
/gem5/src/cpu/
H A Dbase.cc169 const char *cause = "a thread reached the max instruction count"; local
171 scheduleInstStop(tid, p->max_insts_any_thread, cause);
179 const char *cause = "simpoint starting point found"; local
181 scheduleInstStop(0, p->simpoint_start_insts[i], cause);
185 const char *cause = "all threads reached the max instruction count"; local
193 Event *event = new CountedExitEvent(cause, *counter);
207 const char *cause = "a thread reached the max load count"; local
209 scheduleLoadStop(tid, p->max_loads_any_thread, cause);
213 const char *cause = "all threads reached the max load count"; local
220 Event *event = new CountedExitEvent(cause, *counte
[all...]
H A Dbase.hh462 * @param cause Cause to signal in the exit event.
464 void scheduleInstStop(ThreadID tid, Counter insts, const char *cause);
477 * @param cause Cause to signal in the exit event.
479 void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause);
/gem5/src/mem/cache/
H A Dbase.hh968 /** The total number of cycles blocked for each blocked cause. */
970 /** The number of times this cache blocked for each blocked cause. */
973 /** The average number of cycles blocked for each blocked cause. */
1130 * Marks the access path of the cache as blocked for the given cause. This
1132 * @param cause The reason for the cache blocking.
1134 void setBlocked(BlockedCause cause) argument
1136 uint8_t flag = 1 << cause;
1138 blocked_causes[cause]++;
1143 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocke
1153 clearBlocked(BlockedCause cause) argument
[all...]
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64si/
H A Dma_fetch.S131 # verify trap cause

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