1# See LICENSE for license details.
2
3#*****************************************************************************
4# ma_fetch.S
5#-----------------------------------------------------------------------------
6#
7# Test misaligned fetch trap.
8#
9
10#include "riscv_test.h"
11#include "test_macros.h"
12
13RVTEST_RV64S
14RVTEST_CODE_BEGIN
15
16#ifdef __MACHINE_MODE
17  #define sscratch mscratch
18  #define sstatus mstatus
19  #define scause mcause
20  #define sbadaddr mbadaddr
21  #define sepc mepc
22  #define sret mret
23  #define stvec_handler mtvec_handler
24#endif
25
26  .align 2
27  .option norvc
28
29  # Without RVC, the jalr should trap, and the handler will skip ahead.
30  # With RVC, the jalr should not trap, and "j fail" should get skipped.
31  li TESTNUM, 2
32  li t1, 0
33  la t0, 1f
34  jalr t1, t0, 2
351:
36  .option rvc
37  c.j 1f
38  c.j 2f
39  .option norvc
401:
41  j fail
422:
43
44  // This test should pass, since JALR ignores the target LSB
45  li TESTNUM, 3
46  la t0, 1f
47  jalr t1, t0, 1
481:
49  j 1f
50  j fail
511:
52
53  li TESTNUM, 4
54  li t1, 0
55  la t0, 1f
56  jalr t1, t0, 3
571:
58  .option rvc
59  c.j 1f
60  c.j 2f
61  .option norvc
621:
63  j fail
642:
65
66  # Like test 2, but with jal instead of jalr.
67  li TESTNUM, 5
68  li t1, 0
69  la t0, 1f
70  jal t1, 2f
711:
72  .option rvc
73  c.j 1f
742:
75  c.j 2f
76  .option norvc
771:
78  j fail
792:
80
81  # Like test 2, but with a taken branch instead of jalr.
82  li TESTNUM, 6
83  li t1, 0
84  la t0, 1f
85  beqz x0, 2f
861:
87  .option rvc
88  c.j 1f
892:
90  c.j 2f
91  .option norvc
921:
93  j fail
942:
95
96  # Not-taken branches should not trap, even without RVC.
97  li TESTNUM, 7
98  bnez x0, 1f
99  j 2f
100  .option rvc
101  c.j 1f
1021:
103  c.j 1f
104  .option norvc
1051:
106  j fail
1072:
108
109  j pass
110
111  TEST_PASSFAIL
112
113  .align 2
114  .global stvec_handler
115stvec_handler:
116  # tests 2, 4, 5, and 6 should trap
117  li a0, 2
118  beq TESTNUM, a0, 1f
119  li a0, 4
120  beq TESTNUM, a0, 1f
121  li a0, 5
122  beq TESTNUM, a0, 1f
123  li a0, 6
124  beq TESTNUM, a0, 1f
125  j fail
1261:
127
128  # verify that return address was not written
129  bnez t1, fail
130
131  # verify trap cause
132  li a1, CAUSE_MISALIGNED_FETCH
133  csrr a0, scause
134  bne a0, a1, fail
135
136  # verify that epc == &jalr (== t0 - 4)
137  csrr a1, sepc
138  addi a1, a1, 4
139  bne t0, a1, fail
140
141  # verify that badaddr == 0 or badaddr == t0+2.
142  csrr a0, sbadaddr
143  beqz a0, 1f
144  addi a0, a0, -2
145  bne a0, t0, fail
1461:
147
148  addi a1, a1, 12
149  csrw sepc, a1
150  sret
151
152RVTEST_CODE_END
153
154  .data
155RVTEST_DATA_BEGIN
156
157  TEST_DATA
158
159RVTEST_DATA_END
160