Searched refs:cacheEntry (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/sparc/
H A Dtlb.cc78 cacheEntry[0] = NULL;
79 cacheEntry[1] = NULL;
433 if (cacheEntry[0]) {
434 if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) &&
435 cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) {
436 req->setPaddr(cacheEntry[0]->pte.translate(vaddr));
475 cacheEntry[0] = NULL;
525 cacheEntry[0] = e;
570 if (cacheEntry[
[all...]
H A Dtlb.hh198 TlbEntry *cacheEntry[2]; member in class:SparcISA::TLB

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