Lines Matching refs:cacheEntry
78 cacheEntry[0] = NULL;
79 cacheEntry[1] = NULL;
433 if (cacheEntry[0]) {
434 if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) &&
435 cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) {
436 req->setPaddr(cacheEntry[0]->pte.translate(vaddr));
475 cacheEntry[0] = NULL;
525 cacheEntry[0] = e;
570 if (cacheEntry[0]) {
571 TlbEntry *ce = cacheEntry[0];
585 if (cacheEntry[1]) {
586 TlbEntry *ce = cacheEntry[1];
763 cacheEntry[1] = NULL;
764 cacheEntry[0] = NULL;
767 if (cacheEntry[0] != e && cacheEntry[1] != e) {
768 cacheEntry[1] = cacheEntry[0];
769 cacheEntry[0] = e;