Searched refs:bridge (Results 1 - 8 of 8) sorted by relevance
/gem5/src/systemc/tests/tlm/static_extensions/ext2gp/ |
H A D | ext2gp.cpp | 30 adapt_ext2gp<32> bridge("bridge"); 33 initiator.socket(bridge.target_socket); 34 bridge.initiator_socket(target.socket);
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/gem5/src/systemc/tests/tlm/static_extensions/gp2ext/ |
H A D | gp2ext.cpp | 30 adapt_gp2ext<32> bridge("bridge"); 33 initiator.socket(bridge.target_socket); 34 bridge.initiator_socket(target.socket);
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/gem5/src/systemc/tlm_bridge/ |
H A D | gem5_to_tlm.hh | 96 Gem5ToTlmBridge<BITWIDTH> &bridge; member in class:sc_gem5::Gem5ToTlmBridge::BridgeSlavePort 101 return bridge.getAddrRanges(); 106 return bridge.recvAtomic(pkt); 111 return bridge.recvAtomicBackdoor(pkt, backdoor); 116 return bridge.recvFunctional(pkt); 121 return bridge.recvTimingReq(pkt); 126 return bridge.tryTiming(pkt); 131 return bridge.recvTimingSnoopResp(pkt); 133 void recvRespRetry() override { bridge.recvRespRetry(); } 138 SlavePort(name_, nullptr), bridge(bridge [all...] |
H A D | tlm_to_gem5.hh | 98 TlmToGem5Bridge<BITWIDTH> &bridge; member in class:sc_gem5::TlmToGem5Bridge::BridgeMasterPort 103 return bridge.recvTimingResp(pkt); 105 void recvReqRetry() override { bridge.recvReqRetry(); } 106 void recvRangeChange() override { bridge.recvRangeChange(); } 111 MasterPort(name_, nullptr), bridge(bridge_)
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/gem5/src/mem/ |
H A D | bridge.cc | 47 * Implementation of a memory-mapped bridge that connects a master 51 #include "mem/bridge.hh" 62 : SlavePort(_name, &_bridge), bridge(_bridge), masterPort(_masterPort), 73 : MasterPort(_name, &_bridge), bridge(_bridge), slavePort(_slavePort), 105 fatal("Both ports of a bridge must be connected.\n"); 135 // the two sides of the bridge are synchronous) 139 slavePort.schedTimingResp(pkt, bridge.clockEdge(delay) + 188 // payload (unless the two sides of the bridge are 193 masterPort.schedTimingReq(pkt, bridge.clockEdge(delay) + 223 bridge [all...] |
H A D | bridge.hh | 47 * Declaration of a memory-mapped bridge that connects a master 62 * A bridge is used to interface two different crossbars (or in general a 64 * responses. The bridge has a fixed delay for packets passing through 67 * The bridge comprises a slave port and a master port, that buffer 71 * the bridge will delay accepting the packet until space becomes 108 /** The bridge to which this port belongs. */ 109 Bridge& bridge; member in class:Bridge::BridgeSlavePort 112 * Master port on the other side of the bridge. 116 /** Minimum request delay though this bridge. */ 119 /** Address ranges to pass through the bridge */ 229 Bridge& bridge; member in class:Bridge::BridgeMasterPort [all...] |
/gem5/configs/common/ |
H A D | FSConfig.py | 111 # By default the bridge responds to all addresses above the I/O 114 self.bridge = Bridge(delay='50ns', 116 self.bridge.master = self.iobus.slave 117 self.bridge.slave = self.membus.master 161 self.bridge = Bridge(delay='50ns') 167 self.bridge.master = self.iobus.slave 168 self.bridge.slave = self.membus.master 181 self.bridge.ranges = \ 226 self.bridge = Bridge(delay='50ns') 227 self.bridge [all...] |
/gem5/src/dev/arm/ |
H A D | RealView.py | 311 node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle)) 343 node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle)) 583 def attachOnChipIO(self, bus, bridge=None, *args, **kwargs): 585 if bridge: 586 bridge.ranges = self._off_chip_ranges 667 # ranges for the bridge 668 def attachOnChipIO(self, bus, bridge): 676 bridge.ranges = [AddrRange(self.realview_io.pio_addr,
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