Lines Matching refs:bridge
111 # By default the bridge responds to all addresses above the I/O
114 self.bridge = Bridge(delay='50ns',
116 self.bridge.master = self.iobus.slave
117 self.bridge.slave = self.membus.master
161 self.bridge = Bridge(delay='50ns')
167 self.bridge.master = self.iobus.slave
168 self.bridge.slave = self.membus.master
181 self.bridge.ranges = \
226 self.bridge = Bridge(delay='50ns')
227 self.bridge.master = self.iobus.slave
230 self.bridge.slave = self.membus.master
361 self.bridge.ranges = [self.realview.nvmem.range]
371 self.realview.attachOnChipIO(self.membus, self.bridge)
412 self.bridge = Bridge(delay='50ns')
414 self.bridge.master = self.iobus.slave
415 self.bridge.slave = self.membus.master
455 x86_sys.bridge = Bridge(delay='50ns')
456 x86_sys.bridge.master = x86_sys.iobus.slave
457 x86_sys.bridge.slave = x86_sys.membus.master
458 # Allow the bridge to pass through:
461 # 2) the bridge to pass through the IO APIC (two pages, already contained in 1),
464 x86_sys.bridge.ranges = \
473 # Create a bridge from the IO bus to the memory bus to allow access to
635 # specific range can pass though bridge to iobus.