| /gem5/src/sim/ |
| H A D | port.cc | 52 Port::Port(const std::string& _name, PortID _id) : argument
53 portName(_name), id(_id), _peer(nullptr), _connected(false)
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| H A D | port.hh | 91 * @param _id A port identifier for vector ports
93 Port(const std::string& _name, PortID _id);
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| /gem5/src/dev/ |
| H A D | intpin.hh | 47 IntSinkPinBase(const std::string &_name, PortID _id, int num) : argument
48 Port(_name, _id), _number(num)
86 IntSinkPin(const std::string &_name, PortID _id, Device *dev, int num) : argument
87 IntSinkPinBase(_name, _id, num), device(dev) {}
88 IntSinkPin(const std::string &_name, PortID _id, Device *dev) : argument
89 IntSinkPin(_name, _id, dev, _id) {}
99 IntSourcePinBase(const std::string &_name, PortID _id, bool def_state) : argument
100 Port(_name, _id), _state(def_state)
114 IntSourcePin(const std::string &_name, PortID _id, Devic argument
[all...] |
| /gem5/src/mem/ |
| H A D | noncoherent_xbar.hh | 100 NoncoherentXBar &_xbar, PortID _id)
101 : QueuedSlavePort(_name, &_xbar, queue, _id), xbar(_xbar),
153 NoncoherentXBar &_xbar, PortID _id)
154 : MasterPort(_name, &_xbar, _id), xbar(_xbar)
99 NoncoherentXBarSlavePort(const std::string &_name, NoncoherentXBar &_xbar, PortID _id) argument
152 NoncoherentXBarMasterPort(const std::string &_name, NoncoherentXBar &_xbar, PortID _id) argument
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| H A D | port.cc | 57 MasterPort::MasterPort(const std::string& name, SimObject* _owner, PortID _id) argument
58 : Port(name, _id), _slavePort(NULL), owner(*_owner)
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| H A D | coherent_xbar.hh | 104 CoherentXBar &_xbar, PortID _id)
105 : QueuedSlavePort(_name, &_xbar, queue, _id), xbar(_xbar),
163 CoherentXBar &_xbar, PortID _id)
164 : MasterPort(_name, &_xbar, _id), xbar(_xbar)
103 CoherentXBarSlavePort(const std::string &_name, CoherentXBar &_xbar, PortID _id) argument
162 CoherentXBarMasterPort(const std::string &_name, CoherentXBar &_xbar, PortID _id) argument
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| H A D | packet.hh | 820 Packet(const RequestPtr &_req, MemCmd _cmd, int _blkSize, PacketId _id = 0)
821 : cmd(_cmd), id(_id ? _id : (PacketId)_req.get()), req(_req),
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| /gem5/src/systemc/ext/utils/ |
| H A D | sc_report.hh | 89 int get_id() const { return _id; }
102 int _id);
112 int _id; member in class:sc_core::sc_report
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| /gem5/src/systemc/utils/ |
| H A D | sc_report.cc | 43 int _lineNumber, sc_time _time, const char *_processName, int _id) :
46 _time(_time), _processName(_processName), _id(_id)
57 r._lineNumber, r._time, r._processName, r._id)
73 _id = r._id;
41 sc_report(sc_severity _severity, const char *msg_type, const char *msg, int _verbosity, const char *_fileName, int _lineNumber, sc_time _time, const char *_processName, int _id) argument
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| /gem5/src/systemc/ |
| H A D | tlm_port_wrapper.hh | 61 InitiatorSocket &i, const std::string &_name, PortID _id) :
62 Port(_name, _id), _initiator(i)
97 PortID _id) :
98 Port(_name, _id), _target(t)
60 TlmInitiatorBaseWrapper( InitiatorSocket &i, const std::string &_name, PortID _id) argument
96 TlmTargetBaseWrapper(TargetSocket &t, const std::string &_name, PortID _id) argument
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| /gem5/ext/nomali/lib/ |
| H A D | addrspace.cc | 40 AddrSpace::AddrSpace(GPU &_gpu, MMU &_mmu, uint8_t _id) argument
42 id(_id),
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| H A D | jobslot.cc | 46 JobSlot::JobSlot(GPU &_gpu, JobControl &_jc, uint8_t _id) argument
48 id(_id),
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| /gem5/src/cpu/testers/directedtest/ |
| H A D | RubyDirectedTester.hh | 57 PortID _id)
58 : MasterPort(_name, _tester, _id), tester(_tester)
56 CpuPort(const std::string &_name, RubyDirectedTester *_tester, PortID _id) argument
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| /gem5/src/cpu/ |
| H A D | timebuf.hh | 46 int _id; member in class:TimeBuffer
153 _id = -1;
170 _id = id;
175 return _id;
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| /gem5/src/cpu/testers/rubytest/ |
| H A D | RubyTester.hh | 74 CpuPort(const std::string &_name, RubyTester *_tester, PortID _id, argument
76 : MasterPort(_name, _tester, _id), tester(_tester),
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| /gem5/src/dev/arm/ |
| H A D | smmu_v3_ports.cc | 83 PortID _id)
85 QueuedSlavePort(_name, &_ifc, respQueue, _id),
81 SMMUSlavePort(const std::string &_name, SMMUv3SlaveInterface &_ifc, PortID _id) argument
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| H A D | smmu_v3_ports.hh | 89 PortID _id = InvalidPortID);
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| /gem5/src/mem/ruby/slicc_interface/ |
| H A D | AbstractController.hh | 262 SenderState(MachineID _id) : id(_id) argument
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| /gem5/src/base/ |
| H A D | inet.hh | 269 void id(uint16_t _id) { ip_id = htons(_id); } argument
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| /gem5/src/gpu-compute/ |
| H A D | compute_unit.hh | 605 LDSPort(const std::string &_name, ComputeUnit *_cu, PortID _id) argument
606 : MasterPort(_name, _cu, _id), computeUnit(_cu)
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