Searched refs:TlbEntry (Results 1 - 25 of 33) sorted by relevance

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/gem5/src/arch/x86/
H A Dpagetable.cc50 TlbEntry::TlbEntry() function in class:X86ISA::TlbEntry
57 TlbEntry::TlbEntry(Addr asn, Addr _vaddr, Addr _paddr, function in class:X86ISA::TlbEntry
65 TlbEntry::serialize(CheckpointOut &cp) const
80 TlbEntry::unserialize(CheckpointIn &cp)
H A Dtlb.hh63 typedef std::list<TlbEntry *> EntryList;
74 TlbEntry *lookup(Addr va, bool update_lru = true);
96 std::vector<TlbEntry> tlb;
147 TlbEntry *insert(Addr vpn, const TlbEntry &entry);
H A Dpagetable.hh59 struct TlbEntry;
62 typedef Trie<Addr, X86ISA::TlbEntry> TlbEntryTrie;
66 struct TlbEntry : public Serializable struct in namespace:X86ISA
97 TlbEntry(Addr asn, Addr _vaddr, Addr _paddr,
99 TlbEntry();
H A Dtlb.cc96 TlbEntry *
97 TLB::insert(Addr vpn, const TlbEntry &entry)
100 TlbEntry *newEntry = trie.lookup(vpn);
120 TlbEntry *
123 TlbEntry *entry = trie.lookup(va);
164 TlbEntry *entry = trie.lookup(va);
336 TlbEntry *entry = lookup(vaddr);
378 entry = insert(alignedVaddr, TlbEntry(
507 TlbEntry *newEntry = freeList.front();
/gem5/src/arch/alpha/
H A Dtlb.hh51 struct TlbEntry;
77 std::vector<TlbEntry> table; // the Page Table
81 TlbEntry *lookup(Addr vpn, uint8_t asn);
94 TlbEntry &index(bool advance = true);
95 void insert(Addr vaddr, TlbEntry &entry);
124 TlbEntry *EntryCache[3];
128 memset(EntryCache, 0, 3 * sizeof(TlbEntry*));
131 inline TlbEntry *
132 updateCache(TlbEntry *entry) {
H A Dpagetable.cc38 TlbEntry::serialize(CheckpointOut &cp) const
52 TlbEntry::unserialize(CheckpointIn &cp)
H A Dpagetable.hh93 struct TlbEntry : public Serializable struct in namespace:AlphaISA
107 TlbEntry(Addr _asn, Addr _vaddr, Addr _paddr, function in struct:AlphaISA::TlbEntry
122 warn("Alpha TlbEntry does not support uncacheable"
126 TlbEntry() function in struct:AlphaISA::TlbEntry
H A Dtlb.cc163 TlbEntry *
167 TlbEntry *retval = NULL;
188 TlbEntry *entry = &table[index];
248 TLB::insert(Addr addr, TlbEntry &entry)
286 std::fill(table.begin(), table.end(), TlbEntry());
300 TlbEntry *entry = &table[index];
329 TlbEntry *entry = &table[index];
418 TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(),
520 TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), asn);
590 TlbEntry
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/gem5/src/arch/mips/
H A Dpagetable.hh82 struct TlbEntry struct in namespace:MipsISA
85 TlbEntry() {} function in struct:MipsISA::TlbEntry
86 TlbEntry(Addr asn, Addr vaddr, Addr paddr, function in struct:MipsISA::TlbEntry
91 warn("MIPS TlbEntry does not support uncacheable"
/gem5/src/arch/riscv/
H A Dpagetable.hh82 struct TlbEntry struct in namespace:RiscvISA
85 TlbEntry() {} function in struct:RiscvISA::TlbEntry
86 TlbEntry(Addr asn, Addr vaddr, Addr paddr, function in struct:RiscvISA::TlbEntry
91 warn("RISC-V TlbEntry does not support uncacheable"
/gem5/src/arch/arm/
H A Dstage2_lookup.hh63 TlbEntry stage1Te;
70 TlbEntry *stage2Te;
77 Stage2LookUp(TLB *s1Tlb, TLB *s2Tlb, TlbEntry s1Te, const RequestPtr &_req,
90 Fault getTe(ThreadContext *tc, TlbEntry *destTe);
H A Dstage2_lookup.cc57 Stage2LookUp::getTe(ThreadContext *tc, TlbEntry *destTe)
115 if (stage2Te->mtype == TlbEntry::MemoryType::StronglyOrdered ||
116 stage1Te.mtype == TlbEntry::MemoryType::StronglyOrdered) {
117 stage1Te.mtype = TlbEntry::MemoryType::StronglyOrdered;
118 } else if (stage2Te->mtype == TlbEntry::MemoryType::Device ||
119 stage1Te.mtype == TlbEntry::MemoryType::Device) {
120 stage1Te.mtype = TlbEntry::MemoryType::Device;
122 stage1Te.mtype = TlbEntry::MemoryType::Normal;
125 if (stage1Te.mtype == TlbEntry::MemoryType::Normal) {
H A Dtlb.hh82 TlbEntry::DomainType domain) = 0;
98 TlbEntry::DomainType domain,
151 TlbEntry* table; // the Page Table
213 TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp,
232 void insert(Addr vaddr, TlbEntry &pte);
234 Fault getTE(TlbEntry **te, const RequestPtr &req,
239 Fault getResultTe(TlbEntry **te, const RequestPtr &req,
242 bool functional, TlbEntry *mergeTe);
244 Fault checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode);
245 Fault checkPermissions64(TlbEntry *t
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H A Dtlb.cc77 : BaseTLB(p), table(new TlbEntry[p->size]), size(p->size),
127 TlbEntry *e = lookup(va, asid, vmid, isHyp, isSecure, true, false,
151 TlbEntry*
156 TlbEntry *retval = NULL;
167 TlbEntry tmp_entry = table[x];
195 TLB::insert(Addr addr, TlbEntry &entry)
228 TlbEntry *te;
245 TlbEntry *te;
278 TlbEntry *te;
319 TlbEntry *t
[all...]
H A Dtable_walker.cc372 TlbEntry* te = tlb->lookup(currState->vaddr, currState->asid,
482 TlbEntry::DomainType::NoAccess,
502 TlbEntry::DomainType::NoAccess,
520 TlbEntry::DomainType::NoAccess, L1);
616 TlbEntry::DomainType::NoAccess,
640 TlbEntry::DomainType::NoAccess,
662 TlbEntry::DomainType::NoAccess,
688 TlbEntry::DomainType::NoAccess, start_lookup_level);
870 TlbEntry::DomainType::NoAccess,
956 TlbEntry
[all...]
H A Dtable_walker.hh77 virtual TlbEntry::DomainType domain() const = 0;
187 TlbEntry::DomainType domain() const
189 return static_cast<TlbEntry::DomainType>(bits(data, 8, 5));
278 virtual TlbEntry::DomainType domain() const
612 TlbEntry::DomainType domain() const
616 return TlbEntry::DomainType::Client;
915 void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
917 void memAttrsLPAE(ThreadContext *tc, TlbEntry &te,
919 void memAttrsAArch64(ThreadContext *tc, TlbEntry &te,
972 Fault testWalk(Addr pa, Addr size, TlbEntry
[all...]
H A Dpagetable.hh86 struct TlbEntry : public Serializable struct in namespace:ArmISA
150 TlbEntry(Addr _asn, Addr _vaddr, Addr _paddr, function in struct:ArmISA::TlbEntry
164 warn("ARM TlbEntry does not support read-only mappings\n");
167 TlbEntry() : function in struct:ArmISA::TlbEntry
/gem5/src/arch/sparc/
H A Dpagetable.cc39 TlbEntry::serialize(CheckpointOut &cp) const
56 TlbEntry::unserialize(CheckpointIn &cp)
H A Dtlb.hh75 TlbEntry *tlb;
84 std::list<TlbEntry*> freeList;
119 TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0,
198 TlbEntry *cacheEntry[2];
H A Dtlb_map.hh44 typedef std::map<TlbRange, TlbEntry*> RangeMap;
96 insert(TlbRange &r, TlbEntry *d)
H A Dvtophys.cc88 TlbEntry* tbe;
H A Dpagetable.hh228 struct TlbEntry struct in namespace:SparcISA
230 TlbEntry() function in struct:SparcISA::TlbEntry
233 TlbEntry(Addr asn, Addr vaddr, Addr paddr, function in struct:SparcISA::TlbEntry
/gem5/src/gpu-compute/
H A Dgpu_tlb.hh70 typedef std::list<TlbEntry*> EntryList;
121 TlbEntry *lookup(Addr va, bool update_lru=true);
162 std::vector<TlbEntry> tlb;
235 TlbEntry *insert(Addr vpn, TlbEntry &entry);
251 TlbEntry *tlb_entry, Mode mode);
253 void updatePhysAddresses(Addr virt_page_addr, TlbEntry *tlb_entry,
342 TlbEntry *tlbEntry;
H A Dgpu_tlb.cc77 tlb.assign(size, TlbEntry());
156 TlbEntry*
157 GpuTLB::insert(Addr vpn, TlbEntry &entry)
159 TlbEntry *newEntry = nullptr;
212 TlbEntry*
232 TlbEntry *entry = entryList[i].front();
675 TlbEntry *entry = lookup(vaddr, true);
783 TlbEntry *entry = lookup(vaddr);
821 TlbEntry gpuEntry(p->pid(), alignedVaddr,
1068 TlbEntry *entr
[all...]
/gem5/src/arch/power/
H A Dtlb.hh57 struct TlbEntry struct in namespace:PowerISA
61 TlbEntry() function in struct:PowerISA::TlbEntry
65 TlbEntry(Addr asn, Addr vaddr, Addr paddr, function in struct:PowerISA::TlbEntry
70 warn("Power TlbEntry does not support uncacheable"

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