Searched refs:MiscRegOp64 (Results 1 - 3 of 3) sorted by relevance

/gem5/src/arch/arm/insts/
H A Dmisc64.hh115 * Exception level. MiscRegOp64 is providing that feature. Other
121 class MiscRegOp64 : public ArmStaticInst class in inherits:ArmStaticInst
126 MiscRegOp64(const char *mnem, ExtMachInst _machInst, function in class:MiscRegOp64
146 class MiscRegImmOp64 : public MiscRegOp64
155 MiscRegOp64(mnem, _machInst, __opClass, false),
170 class MiscRegRegImmOp64 : public MiscRegOp64
180 MiscRegOp64(mnem, _machInst, __opClass, false),
188 class RegMiscRegImmOp64 : public MiscRegOp64
198 MiscRegOp64(mnem, _machInst, __opClass, true),
206 class MiscRegImplDefined64 : public MiscRegOp64
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H A Dmisc64.cc87 MiscRegOp64::trap(ThreadContext *tc, MiscRegIndex misc_reg,
122 MiscRegOp64::checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
143 MiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
292 MiscRegOp64::checkEL3Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
H A Dmem64.hh48 class SysDC64 : public MiscRegOp64
57 : MiscRegOp64(mnem, _machInst, __opClass, false),

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