Searched refs:MISCREG_MON_NS0_WR (Results 1 - 4 of 4) sorted by relevance

/gem5/src/arch/arm/kvm/
H A Darmv8_cpu.cc385 info[MISCREG_MON_NS0_WR] || info[MISCREG_MON_NS1_WR]);
/gem5/src/arch/arm/
H A Disa.hh271 info[MISCREG_MON_NS0_WR] = v;
H A Dmiscregs.hh975 MISCREG_MON_NS0_WR, enumerator in enum:ArmISA::MiscRegInfo
H A Dmiscregs.cc1046 canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1192 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :

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