Searched refs:GPU (Results 1 - 18 of 18) sorted by relevance

/gem5/ext/nomali/lib/
H A Dgpu.cc27 GPU::GPU(GPUControl &gc, JobControl &jc, MMU &_mmu) function in class:NoMali::GPU
35 GPU::~GPU()
40 GPU::reset()
47 GPU::readReg(RegAddr addr)
55 GPU::writeReg(RegAddr addr, uint32_t value)
64 GPU::readRegRaw(RegAddr addr)
72 GPU::writeRegRaw(RegAddr addr, uint32_t value)
82 GPU
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H A Dgpublock.hh27 class GPU;
30 * Base class for GPU function blocks providing common access
36 GPUBlock(GPU &_gpu);
37 GPUBlock(GPU &_gpu, RegVector::size_type no_regs);
44 * This method is called to simulated a hard reset of the GPU. It
102 /** Reference to the top-level GPU component */
103 GPU &gpu;
105 /** GPU block register file */
121 * Base class for interrupt enabled GPU function blocks.
140 GPUBlockInt(GPU
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H A Dgpu.hh35 * Top-level GPU component (abstract).
37 class GPU class in namespace:NoMali
41 * Instantiate a GPU from a set of functional blocks.
43 * @param gpuControl GPU control implementation.
47 GPU(GPUControl &gpuControl, JobControl &jobControl, MMU &mmu);
48 virtual ~GPU() = 0;
51 * Reset the whole GPU
66 * Read a register value from the GPU.
79 * Write a register value to the GPU.
92 * Read a register value from the GPU withou
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H A Djobcontrol.hh31 class GPU;
34 * Minimal GPU job control implementation.
37 * GPU. The job control block mainly coordinates interrupt delivery
47 JobControl(GPU &_gpu);
H A Dmmu.hh31 class GPU;
36 * This is a dummy implementation of a Midgard GPU MMU block. The only
45 MMU(GPU &_gpu);
H A Dgpucontrol.hh30 class GPU;
33 * Limited GPU control block implementation.
35 * This is a minimal implementation of the Midgard GPU control
37 * dispatch, interrupt handling, and GPU block ready handling.
39 * An actual GPU implementation should specialize this class to setup
53 GPUControl(GPU &_gpu);
65 * @name GPU control block commands
87 * Command handler for GPU-wide hard resets
94 * Command handler for GPU-wide soft resets
151 * GPU contro
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H A Djobslot.hh30 class GPU;
45 JobSlot(GPU &_gpu, JobControl &_jc, uint8_t slot_id);
H A Daddrspace.hh30 class GPU;
45 AddrSpace(GPU &_gpu, MMU &_mmu, uint8_t slot_id);
H A Dmali_midgard.hh35 : public GPU
H A Dgpublock.cc27 GPUBlock::GPUBlock(GPU &_gpu)
32 GPUBlock::GPUBlock(GPU &_gpu, RegVector::size_type no_regs)
80 GPUBlockInt::GPUBlockInt(GPU &_gpu,
H A Dmali_midgard.cc33 : GPU(gpuControl, jobControl, mmu),
H A Daddrspace.cc40 AddrSpace::AddrSpace(GPU &_gpu, MMU &_mmu, uint8_t _id)
H A Dmmu.cc27 MMU::MMU(GPU &_gpu)
H A Dregutils.hh36 * Register blocks within the GPU.
38 * The GPU splits its register space into chunks belonging to specific
42 GPU = 0x0, member in class:NoMali::RegBlock
49 /** Get the register block from a GPU register address */
57 * Get the register address within a GPU block.
59 * This method masks away the block offset from a GPU register
H A Dnomali_api.cc46 void setGpu(NoMali::GPU *gpu) { _gpu = gpu; }
67 NoMali::GPU *_gpu;
247 NoMali::GPU *gpu;
H A Dgpucontrol.cc40 GPUControl::GPUControl(GPU &_gpu)
H A Djobcontrol.cc27 JobControl::JobControl(GPU &_gpu)
H A Djobslot.cc46 JobSlot::JobSlot(GPU &_gpu, JobControl &_jc, uint8_t _id)

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