Searched refs:write (Results 701 - 725 of 747) sorted by relevance

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/gem5/src/arch/arm/
H A Dpmu.cc225 swIncrementEvent->write(val);
298 warn("Not doing anything for write to miscreg %s\n",
805 PMU::SWIncrementEvent::write(uint64_t val) function in class:ArmISA::PMU::SWIncrementEvent
H A Dfaults.hh424 bool write; member in class:ArmISA::AbortFault
436 faultAddr(_faultAddr), OVAddr(0), write(_write),
/gem5/src/cpu/o3/
H A Dlsq_unit.hh165 /** Does this request write all zeros and thus doesn't
361 /** Try to finish a previously blocked write back attempt */
538 // Will also need how many read/write ports the Dcache has. Or keep track
577 Fault write(LSQRequest *req, uint8_t *data, int store_idx);
855 LSQUnit<Impl>::write(LSQRequest *req, uint8_t *data, int store_idx) function in class:LSQUnit
859 DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x | storeHead:%i "
/gem5/src/arch/x86/
H A Dfaults.cc161 else if (code.write)
162 modeStr = "write";
H A Dprocess.cc405 cr0.wp = 1; // Supervisor mode can write read only pages
461 /* Set up the content of the TSS and write it to physical memory. */
622 cr0.wp = 0; // Supervisor mode can write read only pages
654 initVirtMem.write(gdtCurrent, zero);
742 cr0.wp = 0; // Supervisor mode can write read only pages
993 // write contents to stack
1018 initVirtMem.write(auxv_array_end, aux, GuestByteOrder);
1023 initVirtMem.write(auxv_array_end, zero);
/gem5/src/systemc/tests/systemc/1666-2011-compliance/sc_vector/
H A Dsc_vector.cpp287 ports[i % dim].write((j++) % 10); // Use operator[] with vector
/gem5/src/arch/riscv/
H A Dtlb.cc164 warn("Attempted to write at index (%d) beyond TLB size (%d)",
252 .desc("DTB write hits")
257 .desc("DTB write misses")
263 .desc("DTB write accesses")
322 TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
/gem5/src/dev/arm/
H A Dgpu_nomali.cc170 NoMaliGpu::write(PacketPtr pkt) function in class:NoMaliGpu
180 panic("Unexpected GPU register write size: %i\n", size);
182 panic("Unaligned GPU write: %i\n", size);
230 "GPU register write failed");
251 "GPU raw register write failed");
H A Dgic_v2.hh466 Tick write(PacketPtr pkt) override;
492 /** Handle a write to the distributor portion of the GIC
503 /** Handle a write to the cpu portion of the GIC
H A Dufs_device.hh125 /** UFS write transaction flow state machine
565 * Write flash. write the data to the disk image. This function
607 * Sets total amount of write transactions that needs to be made.
639 * write transfer.
836 Tick write(PacketPtr pkt) override;
971 * After a DMA write with data intended for the disk, this function is
H A Dgic_v3_its.hh150 Tick write(PacketPtr pkt) override;
165 // Command read/write, (CREADR, CWRITER)
H A Dgeneric_timer.cc356 warn("Ignoring write to read only count register: %s\n",
597 GenericTimerMem::write(PacketPtr pkt) function in class:GenericTimerMem
683 warn("Ignoring write to unexpected address (0x%x:%i)\n",
694 warn("Ignoring write to unexpected address (0x%x:%i)\n",
833 warn("Unexpected address (0x%x:%i), ignoring write\n", addr, size);
845 warn("Unexpected address (0x%x:%i), ignoring write\n", addr, size);
H A Dvgic.cc84 VGic::write(PacketPtr pkt) function in class:VGic
246 DPRINTF(VGIC, "VGIC VCPU write register %#x <= %#x\n",
275 panic("VGIC VCPU write %#x to unk address %#x\n",
293 DPRINTF(VGIC, "VGIC HVCtrl write register %#x <= %#x\n",
340 panic("VGIC HVCtrl write to bad address %#x\n", daddr);
/gem5/src/dev/net/
H A Di8254xGBe.hh252 // to have to wrap and write more
367 * @param packet ethernet packet to write
373 /** Called by event when dma to write packet is completed
384 // Event to handle issuing header and data write at the same time
479 /** Called by event when dma to write packet is completed
528 Tick write(PacketPtr pkt) override;
/gem5/src/gpu-compute/
H A Ddispatcher.cc157 GpuDispatcher::write(PacketPtr pkt) function in class:GpuDispatcher
184 DPRINTF(GPUDisp, "write register %#x value %#x size=%d\n", offset, data_val,
/gem5/util/
H A Dgem5img.py265 # We lseek to the end of the file and only write one byte there. This
270 os.write(fd, '\0')
/gem5/tests/test-progs/insttest/src/riscv/
H A Drv64i.cpp247 size_t n = write(fd, teststr, sizeof(teststr));
250 }, "open, write");
/gem5/src/dev/alpha/
H A Dtsunami_cchip.cc194 TsunamiCChip::write(PacketPtr pkt) function in class:TsunamiCChip
203 DPRINTF(Tsunami, "write - addr=%#x value=%#x\n",
231 DPRINTF(Tsunami, "dim write resulting in posting dir"
240 DPRINTF(Tsunami, "dim write resulting in clear"
251 panic("TSDEV_CC_CSR write\n");
253 panic("TSDEV_CC_MTR write not implemented\n");
284 panic("TSDEV_CC_MISC write not implemented\n");
291 panic("TSDEV_CC_AARx write not implemeted\n");
332 DPRINTF(Tsunami, "dim write resulting in clear"
346 panic("TSDEV_CC_DIR write no
[all...]
/gem5/src/dev/sparc/
H A Diob.cc171 Iob::write(PacketPtr pkt) function in class:Iob
286 DPRINTF(Iob, "Generating interrupt because of I/O write to cpu: %d vec %d\n",
298 DPRINTF(Iob, "Idling CPU because of I/O write cpu: %d\n", cpu_id);
302 DPRINTF(Iob, "Resuming CPU because of I/O write cpu: %d\n", cpu_id);
/gem5/src/systemc/tests/systemc/examples/aes/
H A Daes.cpp343 Out_wire.write(t_Out_wire);
774 (void)Out_wire.write(t_Out_wire);
/gem5/src/arch/x86/linux/
H A Dprocess.cc138 p.write(addr, fsBase);
146 p.write(addr, gsBase);
262 /* 1 */ SyscallDesc("write", writeFunc<X86Linux64>),
598 /* 4 */ SyscallDesc("write", writeFunc<X86Linux32>),
/gem5/src/dev/storage/
H A Dide_ctrl.cc281 panic("Invalid PCI configuration write "
284 DPRINTF(IdeCtrl, "PCI write offset: %#x size: 1 data: %#x\n",
305 panic("Invalid PCI configuration write "
309 DPRINTF(IdeCtrl, "PCI write offset: %#x size: 2 data: %#x\n",
413 panic("Invalid BMIC write size: %x\n", size);
445 panic("Invalid BMIS write size: %x\n", size);
453 // to reset (set 0) IDEINTS and IDEDMAE, write 1 to each
475 panic("Invalid BMIDTP write size: %x\n", size);
481 panic("IDE controller write of invalid write siz
560 IdeController::write(PacketPtr pkt) function in class:IdeController
[all...]
/gem5/ext/googletest/googletest/src/
H A Dgtest-internal-inl.h252 // function will write over it. If the variable is present, but the file cannot
827 // Protects read and write access to global_test_part_result_reporter_.
1073 if (write(sockfd_, message.c_str(), len) != len) {
/gem5/src/dev/pci/
H A Dcopy_engine.cc292 CopyEngine::write(PacketPtr pkt) function in class:CopyEngine
307 /// Handle write of register here
335 DPRINTF(DMACopyEngine, "Warning, ignorning write to register %x\n",
385 DPRINTF(DMACopyEngine, "Warning, ignorning write to register %x\n",
/gem5/src/sim/
H A Dpseudo_inst.cc561 // copy out data and write to file
564 os->write(buf, len);

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