Searched refs:width (Results 101 - 108 of 108) sorted by relevance
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| /gem5/src/arch/arm/insts/ |
| H A D | macromem.hh | 519 unsigned width, RegIndex rn, RegIndex vd, unsigned regs,
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| /gem5/configs/example/ |
| H A D | apu_se.py | 105 parser.add_option("--glbmem-wr-bus-width", type="int", default=32, \
106 help="VGPR to Coalescer (Global Memory) data bus width in bytes")
107 parser.add_option("--glbmem-rd-bus-width", type="int", default=32, \
108 help="Coalescer to VGPR (Global Memory) data bus width in bytes")
445 system.piobus = IOXBar(width=32, response_latency=0,
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| /gem5/src/arch/arm/ |
| H A D | miscregs_types.hh | 71 Bitfield<4> width; // AArch64 member in namespace:ArmISA
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| H A D | utility.cc | 343 aarch32 = (cpsr.width == 1);
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| H A D | isa.cc | 2030 if (cpsr.width) { // AArch32
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| /gem5/src/cpu/minor/ |
| H A D | execute.cc | 813 if (thread.inputIndex == insts_in->width()) {
824 } while (insts_in && thread.inputIndex < insts_in->width() &&
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| /gem5/src/python/m5/ |
| H A D | params.py | 277 width = int(math.ceil(math.log(len(self))/math.log(10)))
279 v.set_parent(parent, "%s%0*d" % (name, width, i))
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| /gem5/ext/mcpat/cacti/ |
| H A D | Ucache.cc | 264 ptr_array->width = uca->area.w;
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