110152Satgutier@umich.edu/***************************************************************************** 210152Satgutier@umich.edu * McPAT/CACTI 310152Satgutier@umich.edu * SOFTWARE LICENSE AGREEMENT 410152Satgutier@umich.edu * Copyright 2012 Hewlett-Packard Development Company, L.P. 510234Syasuko.eckert@amd.com * Copyright (c) 2010-2013 Advanced Micro Devices, Inc. 610152Satgutier@umich.edu * All Rights Reserved 710152Satgutier@umich.edu * 810152Satgutier@umich.edu * Redistribution and use in source and binary forms, with or without 910152Satgutier@umich.edu * modification, are permitted provided that the following conditions are 1010152Satgutier@umich.edu * met: redistributions of source code must retain the above copyright 1110152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer; 1210152Satgutier@umich.edu * redistributions in binary form must reproduce the above copyright 1310152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer in the 1410152Satgutier@umich.edu * documentation and/or other materials provided with the distribution; 1510152Satgutier@umich.edu * neither the name of the copyright holders nor the names of its 1610152Satgutier@umich.edu * contributors may be used to endorse or promote products derived from 1710152Satgutier@umich.edu * this software without specific prior written permission. 1810152Satgutier@umich.edu 1910152Satgutier@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2010152Satgutier@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2110152Satgutier@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2210152Satgutier@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2310152Satgutier@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2410152Satgutier@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2510152Satgutier@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2610152Satgutier@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2710152Satgutier@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2810152Satgutier@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2910234Syasuko.eckert@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3010152Satgutier@umich.edu * 3110152Satgutier@umich.edu ***************************************************************************/ 3210152Satgutier@umich.edu 3310152Satgutier@umich.edu 3410152Satgutier@umich.edu#include <pthread.h> 3510152Satgutier@umich.edu 3610152Satgutier@umich.edu#include <algorithm> 3710152Satgutier@umich.edu#include <cmath> 3810152Satgutier@umich.edu#include <ctime> 3910152Satgutier@umich.edu#include <iostream> 4010152Satgutier@umich.edu#include <list> 4110152Satgutier@umich.edu 4210152Satgutier@umich.edu#include "Ucache.h" 4310152Satgutier@umich.edu#include "area.h" 4410152Satgutier@umich.edu#include "bank.h" 4510152Satgutier@umich.edu#include "basic_circuit.h" 4610152Satgutier@umich.edu#include "component.h" 4710152Satgutier@umich.edu#include "const.h" 4810152Satgutier@umich.edu#include "decoder.h" 4910152Satgutier@umich.edu#include "parameter.h" 5010152Satgutier@umich.edu#include "subarray.h" 5110152Satgutier@umich.edu#include "uca.h" 5210152Satgutier@umich.edu 5310152Satgutier@umich.eduusing namespace std; 5410152Satgutier@umich.edu 5510152Satgutier@umich.educonst uint32_t nthreads = NTHREADS; 5610152Satgutier@umich.edu 5710152Satgutier@umich.edu 5810234Syasuko.eckert@amd.comvoid min_values_t::update_min_values(const min_values_t * val) { 5910234Syasuko.eckert@amd.com min_delay = (min_delay > val->min_delay) ? val->min_delay : min_delay; 6010234Syasuko.eckert@amd.com min_dyn = (min_dyn > val->min_dyn) ? val->min_dyn : min_dyn; 6110234Syasuko.eckert@amd.com min_leakage = (min_leakage > val->min_leakage) ? val->min_leakage : min_leakage; 6210234Syasuko.eckert@amd.com min_area = (min_area > val->min_area) ? val->min_area : min_area; 6310234Syasuko.eckert@amd.com min_cyc = (min_cyc > val->min_cyc) ? val->min_cyc : min_cyc; 6410152Satgutier@umich.edu} 6510152Satgutier@umich.edu 6610152Satgutier@umich.edu 6710152Satgutier@umich.edu 6810234Syasuko.eckert@amd.comvoid min_values_t::update_min_values(const uca_org_t & res) { 6910234Syasuko.eckert@amd.com min_delay = (min_delay > res.access_time) ? res.access_time : min_delay; 7010234Syasuko.eckert@amd.com min_dyn = (min_dyn > res.power.readOp.dynamic) ? res.power.readOp.dynamic : min_dyn; 7110234Syasuko.eckert@amd.com min_leakage = (min_leakage > res.power.readOp.leakage) ? res.power.readOp.leakage : min_leakage; 7210234Syasuko.eckert@amd.com min_area = (min_area > res.area) ? res.area : min_area; 7310234Syasuko.eckert@amd.com min_cyc = (min_cyc > res.cycle_time) ? res.cycle_time : min_cyc; 7410152Satgutier@umich.edu} 7510152Satgutier@umich.edu 7610234Syasuko.eckert@amd.comvoid min_values_t::update_min_values(const nuca_org_t * res) { 7710234Syasuko.eckert@amd.com min_delay = (min_delay > res->nuca_pda.delay) ? res->nuca_pda.delay : min_delay; 7810234Syasuko.eckert@amd.com min_dyn = (min_dyn > res->nuca_pda.power.readOp.dynamic) ? res->nuca_pda.power.readOp.dynamic : min_dyn; 7910234Syasuko.eckert@amd.com min_leakage = (min_leakage > res->nuca_pda.power.readOp.leakage) ? res->nuca_pda.power.readOp.leakage : min_leakage; 8010234Syasuko.eckert@amd.com min_area = (min_area > res->nuca_pda.area.get_area()) ? res->nuca_pda.area.get_area() : min_area; 8110234Syasuko.eckert@amd.com min_cyc = (min_cyc > res->nuca_pda.cycle_time) ? res->nuca_pda.cycle_time : min_cyc; 8210152Satgutier@umich.edu} 8310152Satgutier@umich.edu 8410234Syasuko.eckert@amd.comvoid min_values_t::update_min_values(const mem_array * res) { 8510234Syasuko.eckert@amd.com min_delay = (min_delay > res->access_time) ? res->access_time : min_delay; 8610234Syasuko.eckert@amd.com min_dyn = (min_dyn > res->power.readOp.dynamic) ? res->power.readOp.dynamic : min_dyn; 8710234Syasuko.eckert@amd.com min_leakage = (min_leakage > res->power.readOp.leakage) ? res->power.readOp.leakage : min_leakage; 8810234Syasuko.eckert@amd.com min_area = (min_area > res->area) ? res->area : min_area; 8910234Syasuko.eckert@amd.com min_cyc = (min_cyc > res->cycle_time) ? res->cycle_time : min_cyc; 9010152Satgutier@umich.edu} 9110152Satgutier@umich.edu 9210152Satgutier@umich.edu 9310152Satgutier@umich.edu 9410234Syasuko.eckert@amd.comvoid * calc_time_mt_wrapper(void * void_obj) { 9510234Syasuko.eckert@amd.com calc_time_mt_wrapper_struct * calc_obj = (calc_time_mt_wrapper_struct *) void_obj; 9610234Syasuko.eckert@amd.com uint32_t tid = calc_obj->tid; 9710234Syasuko.eckert@amd.com list<mem_array *> & data_arr = calc_obj->data_arr; 9810234Syasuko.eckert@amd.com list<mem_array *> & tag_arr = calc_obj->tag_arr; 9910234Syasuko.eckert@amd.com bool is_tag = calc_obj->is_tag; 10010234Syasuko.eckert@amd.com bool pure_ram = calc_obj->pure_ram; 10110234Syasuko.eckert@amd.com bool pure_cam = calc_obj->pure_cam; 10210234Syasuko.eckert@amd.com bool is_main_mem = calc_obj->is_main_mem; 10310234Syasuko.eckert@amd.com double Nspd_min = calc_obj->Nspd_min; 10410234Syasuko.eckert@amd.com min_values_t * data_res = calc_obj->data_res; 10510234Syasuko.eckert@amd.com min_values_t * tag_res = calc_obj->tag_res; 10610152Satgutier@umich.edu 10710234Syasuko.eckert@amd.com data_arr.clear(); 10810234Syasuko.eckert@amd.com data_arr.push_back(new mem_array); 10910234Syasuko.eckert@amd.com tag_arr.clear(); 11010234Syasuko.eckert@amd.com tag_arr.push_back(new mem_array); 11110152Satgutier@umich.edu 11210234Syasuko.eckert@amd.com uint32_t Ndwl_niter = _log2(MAXDATAN) + 1; 11310234Syasuko.eckert@amd.com uint32_t Ndbl_niter = _log2(MAXDATAN) + 1; 11410234Syasuko.eckert@amd.com uint32_t Ndcm_niter = _log2(MAX_COL_MUX) + 1; 11510234Syasuko.eckert@amd.com uint32_t niter = Ndwl_niter * Ndbl_niter * Ndcm_niter; 11610152Satgutier@umich.edu 11710152Satgutier@umich.edu 11810234Syasuko.eckert@amd.com bool is_valid_partition; 11910234Syasuko.eckert@amd.com int wt_min, wt_max; 12010152Satgutier@umich.edu 12110234Syasuko.eckert@amd.com if (g_ip->force_wiretype) { 12210234Syasuko.eckert@amd.com if (g_ip->wt == 0) { 12310234Syasuko.eckert@amd.com wt_min = Low_swing; 12410234Syasuko.eckert@amd.com wt_max = Low_swing; 12510234Syasuko.eckert@amd.com } else { 12610234Syasuko.eckert@amd.com wt_min = Global; 12710234Syasuko.eckert@amd.com wt_max = Low_swing - 1; 12810234Syasuko.eckert@amd.com } 12910234Syasuko.eckert@amd.com } else { 13010234Syasuko.eckert@amd.com wt_min = Global; 13110234Syasuko.eckert@amd.com wt_max = Low_swing; 13210152Satgutier@umich.edu } 13310152Satgutier@umich.edu 13410234Syasuko.eckert@amd.com for (double Nspd = Nspd_min; Nspd <= MAXDATASPD; Nspd *= 2) { 13510234Syasuko.eckert@amd.com for (int wr = wt_min; wr <= wt_max; wr++) { 13610234Syasuko.eckert@amd.com for (uint32_t iter = tid; iter < niter; iter += nthreads) { 13710234Syasuko.eckert@amd.com // reconstruct Ndwl, Ndbl, Ndcm 13810234Syasuko.eckert@amd.com unsigned int Ndwl = 1 << (iter / (Ndbl_niter * Ndcm_niter)); 13910234Syasuko.eckert@amd.com unsigned int Ndbl = 1 << ((iter / (Ndcm_niter)) % Ndbl_niter); 14010234Syasuko.eckert@amd.com unsigned int Ndcm = 1 << (iter % Ndcm_niter); 14110234Syasuko.eckert@amd.com for (unsigned int Ndsam_lev_1 = 1; Ndsam_lev_1 <= MAX_COL_MUX; 14210234Syasuko.eckert@amd.com Ndsam_lev_1 *= 2) { 14310234Syasuko.eckert@amd.com for (unsigned int Ndsam_lev_2 = 1; 14410234Syasuko.eckert@amd.com Ndsam_lev_2 <= MAX_COL_MUX; Ndsam_lev_2 *= 2) { 14510234Syasuko.eckert@amd.com //for debuging 14610234Syasuko.eckert@amd.com if (g_ip->force_cache_config && is_tag == false) { 14710234Syasuko.eckert@amd.com wr = g_ip->wt; 14810234Syasuko.eckert@amd.com Ndwl = g_ip->ndwl; 14910234Syasuko.eckert@amd.com Ndbl = g_ip->ndbl; 15010234Syasuko.eckert@amd.com Ndcm = g_ip->ndcm; 15110234Syasuko.eckert@amd.com if (g_ip->nspd != 0) { 15210234Syasuko.eckert@amd.com Nspd = g_ip->nspd; 15310234Syasuko.eckert@amd.com } 15410234Syasuko.eckert@amd.com if (g_ip->ndsam1 != 0) { 15510234Syasuko.eckert@amd.com Ndsam_lev_1 = g_ip->ndsam1; 15610234Syasuko.eckert@amd.com Ndsam_lev_2 = g_ip->ndsam2; 15710234Syasuko.eckert@amd.com } 15810234Syasuko.eckert@amd.com } 15910152Satgutier@umich.edu 16010234Syasuko.eckert@amd.com if (is_tag == true) { 16110234Syasuko.eckert@amd.com is_valid_partition = calculate_time(is_tag, pure_ram, pure_cam, Nspd, Ndwl, 16210234Syasuko.eckert@amd.com Ndbl, Ndcm, Ndsam_lev_1, Ndsam_lev_2, 16310234Syasuko.eckert@amd.com tag_arr.back(), 0, NULL, NULL, 16410234Syasuko.eckert@amd.com is_main_mem); 16510234Syasuko.eckert@amd.com } 16610234Syasuko.eckert@amd.com // If it's a fully-associative cache, the data array partition parameters are identical to that of 16710234Syasuko.eckert@amd.com // the tag array, so compute data array partition properties also here. 16810234Syasuko.eckert@amd.com if (is_tag == false || g_ip->fully_assoc) { 16910234Syasuko.eckert@amd.com is_valid_partition = calculate_time(is_tag/*false*/, pure_ram, pure_cam, Nspd, Ndwl, 17010234Syasuko.eckert@amd.com Ndbl, Ndcm, Ndsam_lev_1, Ndsam_lev_2, 17110234Syasuko.eckert@amd.com data_arr.back(), 0, NULL, NULL, 17210234Syasuko.eckert@amd.com is_main_mem); 17310234Syasuko.eckert@amd.com } 17410152Satgutier@umich.edu 17510234Syasuko.eckert@amd.com if (is_valid_partition) { 17610234Syasuko.eckert@amd.com if (is_tag == true) { 17710234Syasuko.eckert@amd.com tag_arr.back()->wt = (enum Wire_type) wr; 17810234Syasuko.eckert@amd.com tag_res->update_min_values(tag_arr.back()); 17910234Syasuko.eckert@amd.com tag_arr.push_back(new mem_array); 18010234Syasuko.eckert@amd.com } 18110234Syasuko.eckert@amd.com if (is_tag == false || g_ip->fully_assoc) { 18210234Syasuko.eckert@amd.com data_arr.back()->wt = (enum Wire_type) wr; 18310234Syasuko.eckert@amd.com data_res->update_min_values(data_arr.back()); 18410234Syasuko.eckert@amd.com data_arr.push_back(new mem_array); 18510234Syasuko.eckert@amd.com } 18610234Syasuko.eckert@amd.com } 18710152Satgutier@umich.edu 18810234Syasuko.eckert@amd.com if (g_ip->force_cache_config && is_tag == false) { 18910234Syasuko.eckert@amd.com wr = wt_max; 19010234Syasuko.eckert@amd.com iter = niter; 19110234Syasuko.eckert@amd.com if (g_ip->nspd != 0) { 19210234Syasuko.eckert@amd.com Nspd = MAXDATASPD; 19310234Syasuko.eckert@amd.com } 19410234Syasuko.eckert@amd.com if (g_ip->ndsam1 != 0) { 19510234Syasuko.eckert@amd.com Ndsam_lev_1 = MAX_COL_MUX + 1; 19610234Syasuko.eckert@amd.com Ndsam_lev_2 = MAX_COL_MUX + 1; 19710234Syasuko.eckert@amd.com } 19810234Syasuko.eckert@amd.com } 19910234Syasuko.eckert@amd.com } 20010152Satgutier@umich.edu } 20110152Satgutier@umich.edu } 20210152Satgutier@umich.edu } 20310152Satgutier@umich.edu } 20410152Satgutier@umich.edu 20510234Syasuko.eckert@amd.com delete data_arr.back(); 20610234Syasuko.eckert@amd.com delete tag_arr.back(); 20710234Syasuko.eckert@amd.com data_arr.pop_back(); 20810234Syasuko.eckert@amd.com tag_arr.pop_back(); 20910152Satgutier@umich.edu 21010234Syasuko.eckert@amd.com#ifndef DEBUG 21110234Syasuko.eckert@amd.com pthread_exit(NULL); 21210234Syasuko.eckert@amd.com#else 21310234Syasuko.eckert@amd.com return NULL; 21410234Syasuko.eckert@amd.com#endif 21510152Satgutier@umich.edu} 21610152Satgutier@umich.edu 21710152Satgutier@umich.edu 21810152Satgutier@umich.edu 21910152Satgutier@umich.edubool calculate_time( 22010152Satgutier@umich.edu bool is_tag, 22110152Satgutier@umich.edu int pure_ram, 22210152Satgutier@umich.edu bool pure_cam, 22310152Satgutier@umich.edu double Nspd, 22410152Satgutier@umich.edu unsigned int Ndwl, 22510152Satgutier@umich.edu unsigned int Ndbl, 22610152Satgutier@umich.edu unsigned int Ndcm, 22710152Satgutier@umich.edu unsigned int Ndsam_lev_1, 22810152Satgutier@umich.edu unsigned int Ndsam_lev_2, 22910152Satgutier@umich.edu mem_array *ptr_array, 23010152Satgutier@umich.edu int flag_results_populate, 23110152Satgutier@umich.edu results_mem_array *ptr_results, 23210152Satgutier@umich.edu uca_org_t *ptr_fin_res, 23310234Syasuko.eckert@amd.com bool is_main_mem) { 23410234Syasuko.eckert@amd.com DynamicParameter dyn_p(is_tag, pure_ram, pure_cam, Nspd, Ndwl, Ndbl, Ndcm, Ndsam_lev_1, Ndsam_lev_2, is_main_mem); 23510152Satgutier@umich.edu 23610234Syasuko.eckert@amd.com if (dyn_p.is_valid == false) { 23710234Syasuko.eckert@amd.com return false; 23810152Satgutier@umich.edu } 23910152Satgutier@umich.edu 24010234Syasuko.eckert@amd.com UCA * uca = new UCA(dyn_p); 24110152Satgutier@umich.edu 24210152Satgutier@umich.edu 24310234Syasuko.eckert@amd.com //For the final solution, populate the ptr_results data structure 24410234Syasuko.eckert@amd.com //-- TODO: copy only necessary variables 24510234Syasuko.eckert@amd.com if (flag_results_populate) { 24610234Syasuko.eckert@amd.com } else { 24710234Syasuko.eckert@amd.com int num_act_mats_hor_dir = uca->bank.dp.num_act_mats_hor_dir; 24810234Syasuko.eckert@amd.com int num_mats = uca->bank.dp.num_mats; 24910234Syasuko.eckert@amd.com bool is_fa = uca->bank.dp.fully_assoc; 25010234Syasuko.eckert@amd.com bool pure_cam = uca->bank.dp.pure_cam; 25110234Syasuko.eckert@amd.com ptr_array->Ndwl = Ndwl; 25210234Syasuko.eckert@amd.com ptr_array->Ndbl = Ndbl; 25310234Syasuko.eckert@amd.com ptr_array->Nspd = Nspd; 25410234Syasuko.eckert@amd.com ptr_array->deg_bl_muxing = dyn_p.deg_bl_muxing; 25510234Syasuko.eckert@amd.com ptr_array->Ndsam_lev_1 = Ndsam_lev_1; 25610234Syasuko.eckert@amd.com ptr_array->Ndsam_lev_2 = Ndsam_lev_2; 25710234Syasuko.eckert@amd.com ptr_array->access_time = uca->access_time; 25810234Syasuko.eckert@amd.com ptr_array->cycle_time = uca->cycle_time; 25910234Syasuko.eckert@amd.com ptr_array->multisubbank_interleave_cycle_time = 26010234Syasuko.eckert@amd.com uca->multisubbank_interleave_cycle_time; 26110234Syasuko.eckert@amd.com ptr_array->area_ram_cells = uca->area_all_dataramcells; 26210234Syasuko.eckert@amd.com ptr_array->area = uca->area.get_area(); 26310234Syasuko.eckert@amd.com ptr_array->height = uca->area.h; 26410234Syasuko.eckert@amd.com ptr_array->width = uca->area.w; 26510234Syasuko.eckert@amd.com ptr_array->mat_height = uca->bank.mat.area.h; 26610234Syasuko.eckert@amd.com ptr_array->mat_length = uca->bank.mat.area.w; 26710234Syasuko.eckert@amd.com ptr_array->subarray_height = uca->bank.mat.subarray.area.h; 26810234Syasuko.eckert@amd.com ptr_array->subarray_length = uca->bank.mat.subarray.area.w; 26910234Syasuko.eckert@amd.com ptr_array->power = uca->power; 27010234Syasuko.eckert@amd.com ptr_array->delay_senseamp_mux_decoder = 27110234Syasuko.eckert@amd.com MAX(uca->delay_array_to_sa_mux_lev_1_decoder, 27210234Syasuko.eckert@amd.com uca->delay_array_to_sa_mux_lev_2_decoder); 27310234Syasuko.eckert@amd.com ptr_array->delay_before_subarray_output_driver = 27410234Syasuko.eckert@amd.com uca->delay_before_subarray_output_driver; 27510234Syasuko.eckert@amd.com ptr_array->delay_from_subarray_output_driver_to_output = 27610234Syasuko.eckert@amd.com uca->delay_from_subarray_out_drv_to_out; 27710152Satgutier@umich.edu 27810234Syasuko.eckert@amd.com ptr_array->delay_route_to_bank = uca->htree_in_add->delay; 27910234Syasuko.eckert@amd.com ptr_array->delay_input_htree = uca->bank.htree_in_add->delay; 28010234Syasuko.eckert@amd.com ptr_array->delay_row_predecode_driver_and_block = 28110234Syasuko.eckert@amd.com uca->bank.mat.r_predec->delay; 28210234Syasuko.eckert@amd.com ptr_array->delay_row_decoder = uca->bank.mat.row_dec->delay; 28310234Syasuko.eckert@amd.com ptr_array->delay_bitlines = uca->bank.mat.delay_bitline; 28410234Syasuko.eckert@amd.com ptr_array->delay_matchlines = uca->bank.mat.delay_matchchline; 28510234Syasuko.eckert@amd.com ptr_array->delay_sense_amp = uca->bank.mat.delay_sa; 28610234Syasuko.eckert@amd.com ptr_array->delay_subarray_output_driver = 28710234Syasuko.eckert@amd.com uca->bank.mat.delay_subarray_out_drv_htree; 28810234Syasuko.eckert@amd.com ptr_array->delay_dout_htree = uca->bank.htree_out_data->delay; 28910234Syasuko.eckert@amd.com ptr_array->delay_comparator = uca->bank.mat.delay_comparator; 29010152Satgutier@umich.edu 29110234Syasuko.eckert@amd.com ptr_array->all_banks_height = uca->area.h; 29210234Syasuko.eckert@amd.com ptr_array->all_banks_width = uca->area.w; 29310234Syasuko.eckert@amd.com ptr_array->area_efficiency = uca->area_all_dataramcells * 100 / 29410234Syasuko.eckert@amd.com (uca->area.get_area()); 29510152Satgutier@umich.edu 29610234Syasuko.eckert@amd.com ptr_array->power_routing_to_bank = uca->power_routing_to_bank; 29710234Syasuko.eckert@amd.com ptr_array->power_addr_input_htree = uca->bank.htree_in_add->power; 29810234Syasuko.eckert@amd.com ptr_array->power_data_input_htree = uca->bank.htree_in_data->power; 29910234Syasuko.eckert@amd.com ptr_array->power_data_output_htree = uca->bank.htree_out_data->power; 30010234Syasuko.eckert@amd.com 30110234Syasuko.eckert@amd.com ptr_array->power_row_predecoder_drivers = 30210234Syasuko.eckert@amd.com uca->bank.mat.r_predec->driver_power; 30310234Syasuko.eckert@amd.com ptr_array->power_row_predecoder_drivers.readOp.dynamic *= 30410234Syasuko.eckert@amd.com num_act_mats_hor_dir; 30510234Syasuko.eckert@amd.com ptr_array->power_row_predecoder_drivers.writeOp.dynamic *= 30610234Syasuko.eckert@amd.com num_act_mats_hor_dir; 30710234Syasuko.eckert@amd.com ptr_array->power_row_predecoder_drivers.searchOp.dynamic *= 30810234Syasuko.eckert@amd.com num_act_mats_hor_dir; 30910234Syasuko.eckert@amd.com 31010234Syasuko.eckert@amd.com ptr_array->power_row_predecoder_blocks = 31110234Syasuko.eckert@amd.com uca->bank.mat.r_predec->block_power; 31210234Syasuko.eckert@amd.com ptr_array->power_row_predecoder_blocks.readOp.dynamic *= 31310234Syasuko.eckert@amd.com num_act_mats_hor_dir; 31410234Syasuko.eckert@amd.com ptr_array->power_row_predecoder_blocks.writeOp.dynamic *= 31510234Syasuko.eckert@amd.com num_act_mats_hor_dir; 31610234Syasuko.eckert@amd.com ptr_array->power_row_predecoder_blocks.searchOp.dynamic *= 31710234Syasuko.eckert@amd.com num_act_mats_hor_dir; 31810234Syasuko.eckert@amd.com 31910234Syasuko.eckert@amd.com ptr_array->power_row_decoders = uca->bank.mat.power_row_decoders; 32010234Syasuko.eckert@amd.com ptr_array->power_row_decoders.readOp.dynamic *= num_act_mats_hor_dir; 32110234Syasuko.eckert@amd.com ptr_array->power_row_decoders.writeOp.dynamic *= num_act_mats_hor_dir; 32210234Syasuko.eckert@amd.com ptr_array->power_row_decoders.searchOp.dynamic *= num_act_mats_hor_dir; 32310234Syasuko.eckert@amd.com 32410234Syasuko.eckert@amd.com ptr_array->power_bit_mux_predecoder_drivers = 32510234Syasuko.eckert@amd.com uca->bank.mat.b_mux_predec->driver_power; 32610234Syasuko.eckert@amd.com ptr_array->power_bit_mux_predecoder_drivers.readOp.dynamic *= 32710234Syasuko.eckert@amd.com num_act_mats_hor_dir; 32810234Syasuko.eckert@amd.com ptr_array->power_bit_mux_predecoder_drivers.writeOp.dynamic *= 32910234Syasuko.eckert@amd.com num_act_mats_hor_dir; 33010234Syasuko.eckert@amd.com ptr_array->power_bit_mux_predecoder_drivers.searchOp.dynamic *= 33110234Syasuko.eckert@amd.com num_act_mats_hor_dir; 33210234Syasuko.eckert@amd.com 33310234Syasuko.eckert@amd.com ptr_array->power_bit_mux_predecoder_blocks = 33410234Syasuko.eckert@amd.com uca->bank.mat.b_mux_predec->block_power; 33510234Syasuko.eckert@amd.com ptr_array->power_bit_mux_predecoder_blocks.readOp.dynamic *= 33610234Syasuko.eckert@amd.com num_act_mats_hor_dir; 33710234Syasuko.eckert@amd.com ptr_array->power_bit_mux_predecoder_blocks.writeOp.dynamic *= 33810234Syasuko.eckert@amd.com num_act_mats_hor_dir; 33910234Syasuko.eckert@amd.com ptr_array->power_bit_mux_predecoder_blocks.searchOp.dynamic *= 34010234Syasuko.eckert@amd.com num_act_mats_hor_dir; 34110234Syasuko.eckert@amd.com 34210234Syasuko.eckert@amd.com ptr_array->power_bit_mux_decoders = uca->bank.mat.power_bit_mux_decoders; 34310234Syasuko.eckert@amd.com ptr_array->power_bit_mux_decoders.readOp.dynamic *= num_act_mats_hor_dir; 34410234Syasuko.eckert@amd.com ptr_array->power_bit_mux_decoders.writeOp.dynamic *= 34510234Syasuko.eckert@amd.com num_act_mats_hor_dir; 34610234Syasuko.eckert@amd.com ptr_array->power_bit_mux_decoders.searchOp.dynamic *= 34710234Syasuko.eckert@amd.com num_act_mats_hor_dir; 34810234Syasuko.eckert@amd.com 34910234Syasuko.eckert@amd.com ptr_array->power_senseamp_mux_lev_1_predecoder_drivers = 35010234Syasuko.eckert@amd.com uca->bank.mat.sa_mux_lev_1_predec->driver_power; 35110234Syasuko.eckert@amd.com ptr_array->power_senseamp_mux_lev_1_predecoder_drivers .readOp.dynamic *= 35210234Syasuko.eckert@amd.com num_act_mats_hor_dir; 35310234Syasuko.eckert@amd.com ptr_array->power_senseamp_mux_lev_1_predecoder_drivers .writeOp.dynamic *= 35410234Syasuko.eckert@amd.com num_act_mats_hor_dir; 35510234Syasuko.eckert@amd.com ptr_array->power_senseamp_mux_lev_1_predecoder_drivers .searchOp.dynamic *= 35610234Syasuko.eckert@amd.com num_act_mats_hor_dir; 35710234Syasuko.eckert@amd.com 35810234Syasuko.eckert@amd.com ptr_array->power_senseamp_mux_lev_1_predecoder_blocks = 35910234Syasuko.eckert@amd.com uca->bank.mat.sa_mux_lev_1_predec->block_power; 36010234Syasuko.eckert@amd.com ptr_array->power_senseamp_mux_lev_1_predecoder_blocks.readOp.dynamic *= 36110234Syasuko.eckert@amd.com num_act_mats_hor_dir; 36210234Syasuko.eckert@amd.com ptr_array->power_senseamp_mux_lev_1_predecoder_blocks.writeOp.dynamic *= 36310234Syasuko.eckert@amd.com num_act_mats_hor_dir; 36410234Syasuko.eckert@amd.com ptr_array->power_senseamp_mux_lev_1_predecoder_blocks.searchOp.dynamic *= 36510234Syasuko.eckert@amd.com num_act_mats_hor_dir; 36610234Syasuko.eckert@amd.com 36710234Syasuko.eckert@amd.com ptr_array->power_senseamp_mux_lev_1_decoders = 36810234Syasuko.eckert@amd.com uca->bank.mat.power_sa_mux_lev_1_decoders; 36910234Syasuko.eckert@amd.com ptr_array->power_senseamp_mux_lev_1_decoders.readOp.dynamic *= 37010234Syasuko.eckert@amd.com num_act_mats_hor_dir; 37110234Syasuko.eckert@amd.com ptr_array->power_senseamp_mux_lev_1_decoders.writeOp.dynamic *= 37210234Syasuko.eckert@amd.com num_act_mats_hor_dir; 37310234Syasuko.eckert@amd.com ptr_array->power_senseamp_mux_lev_1_decoders.searchOp.dynamic *= 37410234Syasuko.eckert@amd.com num_act_mats_hor_dir; 37510234Syasuko.eckert@amd.com 37610234Syasuko.eckert@amd.com ptr_array->power_senseamp_mux_lev_2_predecoder_drivers = 37710234Syasuko.eckert@amd.com uca->bank.mat.sa_mux_lev_2_predec->driver_power; 37810234Syasuko.eckert@amd.com ptr_array->power_senseamp_mux_lev_2_predecoder_drivers.readOp.dynamic *= 37910234Syasuko.eckert@amd.com num_act_mats_hor_dir; 38010234Syasuko.eckert@amd.com ptr_array->power_senseamp_mux_lev_2_predecoder_drivers.writeOp.dynamic *= 38110234Syasuko.eckert@amd.com num_act_mats_hor_dir; 38210234Syasuko.eckert@amd.com ptr_array->power_senseamp_mux_lev_2_predecoder_drivers.searchOp.dynamic *= 38310234Syasuko.eckert@amd.com num_act_mats_hor_dir; 38410234Syasuko.eckert@amd.com 38510234Syasuko.eckert@amd.com ptr_array->power_senseamp_mux_lev_2_predecoder_blocks = 38610234Syasuko.eckert@amd.com uca->bank.mat.sa_mux_lev_2_predec->block_power; 38710234Syasuko.eckert@amd.com ptr_array->power_senseamp_mux_lev_2_predecoder_blocks.readOp.dynamic *= 38810234Syasuko.eckert@amd.com num_act_mats_hor_dir; 38910234Syasuko.eckert@amd.com ptr_array->power_senseamp_mux_lev_2_predecoder_blocks.writeOp.dynamic *= 39010234Syasuko.eckert@amd.com num_act_mats_hor_dir; 39110234Syasuko.eckert@amd.com ptr_array->power_senseamp_mux_lev_2_predecoder_blocks.searchOp.dynamic *= 39210234Syasuko.eckert@amd.com num_act_mats_hor_dir; 39310234Syasuko.eckert@amd.com 39410234Syasuko.eckert@amd.com ptr_array->power_senseamp_mux_lev_2_decoders = 39510234Syasuko.eckert@amd.com uca->bank.mat.power_sa_mux_lev_2_decoders; 39610234Syasuko.eckert@amd.com ptr_array->power_senseamp_mux_lev_2_decoders .readOp.dynamic *= 39710234Syasuko.eckert@amd.com num_act_mats_hor_dir; 39810234Syasuko.eckert@amd.com ptr_array->power_senseamp_mux_lev_2_decoders .writeOp.dynamic *= 39910234Syasuko.eckert@amd.com num_act_mats_hor_dir; 40010234Syasuko.eckert@amd.com ptr_array->power_senseamp_mux_lev_2_decoders .searchOp.dynamic *= 40110234Syasuko.eckert@amd.com num_act_mats_hor_dir; 40210234Syasuko.eckert@amd.com 40310234Syasuko.eckert@amd.com ptr_array->power_bitlines = uca->bank.mat.power_bitline; 40410234Syasuko.eckert@amd.com ptr_array->power_bitlines.readOp.dynamic *= num_act_mats_hor_dir; 40510234Syasuko.eckert@amd.com ptr_array->power_bitlines.writeOp.dynamic *= num_act_mats_hor_dir; 40610234Syasuko.eckert@amd.com ptr_array->power_bitlines.searchOp.dynamic *= num_act_mats_hor_dir; 40710234Syasuko.eckert@amd.com 40810234Syasuko.eckert@amd.com ptr_array->power_sense_amps = uca->bank.mat.power_sa; 40910234Syasuko.eckert@amd.com ptr_array->power_sense_amps.readOp.dynamic *= num_act_mats_hor_dir; 41010234Syasuko.eckert@amd.com ptr_array->power_sense_amps.writeOp.dynamic *= num_act_mats_hor_dir; 41110234Syasuko.eckert@amd.com ptr_array->power_sense_amps.searchOp.dynamic *= num_act_mats_hor_dir; 41210234Syasuko.eckert@amd.com 41310234Syasuko.eckert@amd.com ptr_array->power_prechg_eq_drivers = 41410234Syasuko.eckert@amd.com uca->bank.mat.power_bl_precharge_eq_drv; 41510234Syasuko.eckert@amd.com ptr_array->power_prechg_eq_drivers.readOp.dynamic *= 41610234Syasuko.eckert@amd.com num_act_mats_hor_dir; 41710234Syasuko.eckert@amd.com ptr_array->power_prechg_eq_drivers.writeOp.dynamic *= 41810234Syasuko.eckert@amd.com num_act_mats_hor_dir; 41910234Syasuko.eckert@amd.com ptr_array->power_prechg_eq_drivers.searchOp.dynamic *= 42010234Syasuko.eckert@amd.com num_act_mats_hor_dir; 42110234Syasuko.eckert@amd.com 42210234Syasuko.eckert@amd.com ptr_array->power_output_drivers_at_subarray = 42310234Syasuko.eckert@amd.com uca->bank.mat.power_subarray_out_drv; 42410234Syasuko.eckert@amd.com ptr_array->power_output_drivers_at_subarray.readOp.dynamic *= 42510234Syasuko.eckert@amd.com num_act_mats_hor_dir; 42610234Syasuko.eckert@amd.com ptr_array->power_output_drivers_at_subarray.writeOp.dynamic *= 42710234Syasuko.eckert@amd.com num_act_mats_hor_dir; 42810234Syasuko.eckert@amd.com ptr_array->power_output_drivers_at_subarray.searchOp.dynamic *= 42910234Syasuko.eckert@amd.com num_act_mats_hor_dir; 43010234Syasuko.eckert@amd.com 43110234Syasuko.eckert@amd.com ptr_array->power_comparators = uca->bank.mat.power_comparator; 43210234Syasuko.eckert@amd.com ptr_array->power_comparators.readOp.dynamic *= num_act_mats_hor_dir; 43310234Syasuko.eckert@amd.com ptr_array->power_comparators.writeOp.dynamic *= num_act_mats_hor_dir; 43410234Syasuko.eckert@amd.com ptr_array->power_comparators.searchOp.dynamic *= num_act_mats_hor_dir; 43510234Syasuko.eckert@amd.com 43610234Syasuko.eckert@amd.com if (is_fa || pure_cam) { 43710234Syasuko.eckert@amd.com ptr_array->power_htree_in_search = 43810234Syasuko.eckert@amd.com uca->bank.htree_in_search->power; 43910234Syasuko.eckert@amd.com ptr_array->power_htree_out_search = 44010234Syasuko.eckert@amd.com uca->bank.htree_out_search->power; 44110234Syasuko.eckert@amd.com ptr_array->power_searchline = uca->bank.mat.power_searchline; 44210234Syasuko.eckert@amd.com ptr_array->power_searchline.searchOp.dynamic *= num_mats; 44310234Syasuko.eckert@amd.com ptr_array->power_searchline_precharge = 44410234Syasuko.eckert@amd.com uca->bank.mat.power_searchline_precharge; 44510234Syasuko.eckert@amd.com ptr_array->power_searchline_precharge.searchOp.dynamic *= num_mats; 44610234Syasuko.eckert@amd.com ptr_array->power_matchlines = uca->bank.mat.power_matchline; 44710234Syasuko.eckert@amd.com ptr_array->power_matchlines.searchOp.dynamic *= num_mats; 44810234Syasuko.eckert@amd.com ptr_array->power_matchline_precharge = 44910234Syasuko.eckert@amd.com uca->bank.mat.power_matchline_precharge; 45010234Syasuko.eckert@amd.com ptr_array->power_matchline_precharge.searchOp.dynamic *= num_mats; 45110234Syasuko.eckert@amd.com ptr_array->power_matchline_to_wordline_drv = 45210234Syasuko.eckert@amd.com uca->bank.mat.power_ml_to_ram_wl_drv; 45310234Syasuko.eckert@amd.com } 45410234Syasuko.eckert@amd.com 45510234Syasuko.eckert@amd.com ptr_array->activate_energy = uca->activate_energy; 45610234Syasuko.eckert@amd.com ptr_array->read_energy = uca->read_energy; 45710234Syasuko.eckert@amd.com ptr_array->write_energy = uca->write_energy; 45810234Syasuko.eckert@amd.com ptr_array->precharge_energy = uca->precharge_energy; 45910234Syasuko.eckert@amd.com ptr_array->refresh_power = uca->refresh_power; 46010234Syasuko.eckert@amd.com ptr_array->leak_power_subbank_closed_page = 46110234Syasuko.eckert@amd.com uca->leak_power_subbank_closed_page; 46210234Syasuko.eckert@amd.com ptr_array->leak_power_subbank_open_page = 46310234Syasuko.eckert@amd.com uca->leak_power_subbank_open_page; 46410234Syasuko.eckert@amd.com ptr_array->leak_power_request_and_reply_networks = 46510234Syasuko.eckert@amd.com uca->leak_power_request_and_reply_networks; 46610234Syasuko.eckert@amd.com 46710234Syasuko.eckert@amd.com ptr_array->precharge_delay = uca->precharge_delay; 46810234Syasuko.eckert@amd.com } 46910234Syasuko.eckert@amd.com 47010234Syasuko.eckert@amd.com 47110234Syasuko.eckert@amd.com delete uca; 47210234Syasuko.eckert@amd.com return true; 47310152Satgutier@umich.edu} 47410152Satgutier@umich.edu 47510152Satgutier@umich.edu 47610152Satgutier@umich.edu 47710234Syasuko.eckert@amd.combool check_uca_org(uca_org_t & u, min_values_t *minval) { 47810234Syasuko.eckert@amd.com if (((u.access_time - minval->min_delay) * 100 / minval->min_delay) > 47910234Syasuko.eckert@amd.com g_ip->delay_dev) { 48010234Syasuko.eckert@amd.com return false; 48110234Syasuko.eckert@amd.com } 48210234Syasuko.eckert@amd.com if (((u.power.readOp.dynamic - minval->min_dyn) / minval->min_dyn)*100 > 48310234Syasuko.eckert@amd.com g_ip->dynamic_power_dev) { 48410234Syasuko.eckert@amd.com return false; 48510234Syasuko.eckert@amd.com } 48610234Syasuko.eckert@amd.com if (((u.power.readOp.leakage - minval->min_leakage) / 48710234Syasuko.eckert@amd.com minval->min_leakage) * 100 > 48810234Syasuko.eckert@amd.com g_ip->leakage_power_dev) { 48910234Syasuko.eckert@amd.com return false; 49010234Syasuko.eckert@amd.com } 49110234Syasuko.eckert@amd.com if (((u.cycle_time - minval->min_cyc) / minval->min_cyc)*100 > 49210234Syasuko.eckert@amd.com g_ip->cycle_time_dev) { 49310234Syasuko.eckert@amd.com return false; 49410234Syasuko.eckert@amd.com } 49510234Syasuko.eckert@amd.com if (((u.area - minval->min_area) / minval->min_area)*100 > 49610234Syasuko.eckert@amd.com g_ip->area_dev) { 49710234Syasuko.eckert@amd.com return false; 49810234Syasuko.eckert@amd.com } 49910234Syasuko.eckert@amd.com return true; 50010152Satgutier@umich.edu} 50110152Satgutier@umich.edu 50210234Syasuko.eckert@amd.combool check_mem_org(mem_array & u, const min_values_t *minval) { 50310234Syasuko.eckert@amd.com if (((u.access_time - minval->min_delay) * 100 / minval->min_delay) > 50410234Syasuko.eckert@amd.com g_ip->delay_dev) { 50510234Syasuko.eckert@amd.com return false; 50610234Syasuko.eckert@amd.com } 50710234Syasuko.eckert@amd.com if (((u.power.readOp.dynamic - minval->min_dyn) / minval->min_dyn)*100 > 50810234Syasuko.eckert@amd.com g_ip->dynamic_power_dev) { 50910234Syasuko.eckert@amd.com return false; 51010234Syasuko.eckert@amd.com } 51110234Syasuko.eckert@amd.com if (((u.power.readOp.leakage - minval->min_leakage) / 51210234Syasuko.eckert@amd.com minval->min_leakage) * 100 > 51310234Syasuko.eckert@amd.com g_ip->leakage_power_dev) { 51410234Syasuko.eckert@amd.com return false; 51510234Syasuko.eckert@amd.com } 51610234Syasuko.eckert@amd.com if (((u.cycle_time - minval->min_cyc) / minval->min_cyc) * 100 > 51710234Syasuko.eckert@amd.com g_ip->cycle_time_dev) { 51810234Syasuko.eckert@amd.com return false; 51910234Syasuko.eckert@amd.com } 52010234Syasuko.eckert@amd.com if (((u.area - minval->min_area) / minval->min_area) * 100 > 52110234Syasuko.eckert@amd.com g_ip->area_dev) { 52210234Syasuko.eckert@amd.com return false; 52310234Syasuko.eckert@amd.com } 52410234Syasuko.eckert@amd.com return true; 52510152Satgutier@umich.edu} 52610152Satgutier@umich.edu 52710152Satgutier@umich.edu 52810152Satgutier@umich.edu 52910152Satgutier@umich.edu 53010234Syasuko.eckert@amd.comvoid find_optimal_uca(uca_org_t *res, min_values_t * minval, 53110234Syasuko.eckert@amd.com list<uca_org_t> & ulist) { 53210234Syasuko.eckert@amd.com double cost = 0; 53310234Syasuko.eckert@amd.com double min_cost = BIGNUM; 53410234Syasuko.eckert@amd.com float d, a, dp, lp, c; 53510152Satgutier@umich.edu 53610234Syasuko.eckert@amd.com dp = g_ip->dynamic_power_wt; 53710234Syasuko.eckert@amd.com lp = g_ip->leakage_power_wt; 53810234Syasuko.eckert@amd.com a = g_ip->area_wt; 53910234Syasuko.eckert@amd.com d = g_ip->delay_wt; 54010234Syasuko.eckert@amd.com c = g_ip->cycle_time_wt; 54110152Satgutier@umich.edu 54210234Syasuko.eckert@amd.com if (ulist.empty() == true) { 54310234Syasuko.eckert@amd.com cout << "ERROR: no valid cache organizations found" << endl; 54410234Syasuko.eckert@amd.com exit(0); 54510234Syasuko.eckert@amd.com } 54610152Satgutier@umich.edu 54710234Syasuko.eckert@amd.com for (list<uca_org_t>::iterator niter = ulist.begin(); niter != ulist.end(); 54810234Syasuko.eckert@amd.com niter++) { 54910234Syasuko.eckert@amd.com if (g_ip->ed == 1) { 55010234Syasuko.eckert@amd.com cost = ((niter)->access_time / minval->min_delay) * 55110234Syasuko.eckert@amd.com ((niter)->power.readOp.dynamic / minval->min_dyn); 55210234Syasuko.eckert@amd.com if (min_cost > cost) { 55310234Syasuko.eckert@amd.com min_cost = cost; 55410234Syasuko.eckert@amd.com *res = (*(niter)); 55510234Syasuko.eckert@amd.com } 55610234Syasuko.eckert@amd.com } else if (g_ip->ed == 2) { 55710234Syasuko.eckert@amd.com cost = ((niter)->access_time / minval->min_delay) * 55810234Syasuko.eckert@amd.com ((niter)->access_time / minval->min_delay) * 55910234Syasuko.eckert@amd.com ((niter)->power.readOp.dynamic / minval->min_dyn); 56010234Syasuko.eckert@amd.com if (min_cost > cost) { 56110234Syasuko.eckert@amd.com min_cost = cost; 56210234Syasuko.eckert@amd.com *res = (*(niter)); 56310234Syasuko.eckert@amd.com } 56410234Syasuko.eckert@amd.com } else { 56510234Syasuko.eckert@amd.com /* 56610234Syasuko.eckert@amd.com * check whether the current organization 56710234Syasuko.eckert@amd.com * meets the input deviation constraints 56810234Syasuko.eckert@amd.com */ 56910234Syasuko.eckert@amd.com bool v = check_uca_org(*niter, minval); 57010234Syasuko.eckert@amd.com 57110234Syasuko.eckert@amd.com if (v) { 57210234Syasuko.eckert@amd.com cost = (d * ((niter)->access_time / minval->min_delay) + 57310234Syasuko.eckert@amd.com c * ((niter)->cycle_time / minval->min_cyc) + 57410234Syasuko.eckert@amd.com dp * ((niter)->power.readOp.dynamic / minval->min_dyn) + 57510234Syasuko.eckert@amd.com lp * 57610234Syasuko.eckert@amd.com ((niter)->power.readOp.leakage / minval->min_leakage) + 57710234Syasuko.eckert@amd.com a * ((niter)->area / minval->min_area)); 57810234Syasuko.eckert@amd.com 57910234Syasuko.eckert@amd.com if (min_cost > cost) { 58010234Syasuko.eckert@amd.com min_cost = cost; 58110234Syasuko.eckert@amd.com *res = (*(niter)); 58210234Syasuko.eckert@amd.com niter = ulist.erase(niter); 58310234Syasuko.eckert@amd.com if (niter != ulist.begin()) 58410234Syasuko.eckert@amd.com niter--; 58510234Syasuko.eckert@amd.com } 58610234Syasuko.eckert@amd.com } else { 58710234Syasuko.eckert@amd.com niter = ulist.erase(niter); 58810234Syasuko.eckert@amd.com if (niter != ulist.begin()) 58910234Syasuko.eckert@amd.com niter--; 59010234Syasuko.eckert@amd.com } 59110234Syasuko.eckert@amd.com } 59210152Satgutier@umich.edu } 59310234Syasuko.eckert@amd.com 59410234Syasuko.eckert@amd.com if (min_cost == BIGNUM) { 59510234Syasuko.eckert@amd.com cout << "ERROR: no cache organizations met optimization criteria" 59610234Syasuko.eckert@amd.com << endl; 59710234Syasuko.eckert@amd.com exit(0); 59810152Satgutier@umich.edu } 59910152Satgutier@umich.edu} 60010152Satgutier@umich.edu 60110152Satgutier@umich.edu 60210152Satgutier@umich.edu 60310234Syasuko.eckert@amd.comvoid filter_tag_arr(const min_values_t * min, list<mem_array *> & list) { 60410234Syasuko.eckert@amd.com double cost = BIGNUM; 60510234Syasuko.eckert@amd.com double cur_cost; 60610234Syasuko.eckert@amd.com double wt_delay = g_ip->delay_wt; 60710234Syasuko.eckert@amd.com double wt_dyn = g_ip->dynamic_power_wt; 60810234Syasuko.eckert@amd.com double wt_leakage = g_ip->leakage_power_wt; 60910234Syasuko.eckert@amd.com double wt_cyc = g_ip->cycle_time_wt; 61010234Syasuko.eckert@amd.com double wt_area = g_ip->area_wt; 61110234Syasuko.eckert@amd.com mem_array * res = NULL; 61210152Satgutier@umich.edu 61310234Syasuko.eckert@amd.com if (list.empty() == true) { 61410234Syasuko.eckert@amd.com cout << "ERROR: no valid tag organizations found" << endl; 61510234Syasuko.eckert@amd.com exit(1); 61610234Syasuko.eckert@amd.com } 61710152Satgutier@umich.edu 61810152Satgutier@umich.edu 61910234Syasuko.eckert@amd.com while (list.empty() != true) { 62010234Syasuko.eckert@amd.com bool v = check_mem_org(*list.back(), min); 62110234Syasuko.eckert@amd.com if (v) { 62210234Syasuko.eckert@amd.com cur_cost = wt_delay * (list.back()->access_time / min->min_delay) + 62310234Syasuko.eckert@amd.com wt_dyn * (list.back()->power.readOp.dynamic / 62410234Syasuko.eckert@amd.com min->min_dyn) + 62510234Syasuko.eckert@amd.com wt_leakage * (list.back()->power.readOp.leakage / 62610234Syasuko.eckert@amd.com min->min_leakage) + 62710234Syasuko.eckert@amd.com wt_area * (list.back()->area / min->min_area) + 62810234Syasuko.eckert@amd.com wt_cyc * (list.back()->cycle_time / min->min_cyc); 62910234Syasuko.eckert@amd.com } else { 63010234Syasuko.eckert@amd.com cur_cost = BIGNUM; 63110234Syasuko.eckert@amd.com } 63210234Syasuko.eckert@amd.com if (cur_cost < cost) { 63310234Syasuko.eckert@amd.com if (res != NULL) { 63410234Syasuko.eckert@amd.com delete res; 63510234Syasuko.eckert@amd.com } 63610234Syasuko.eckert@amd.com cost = cur_cost; 63710234Syasuko.eckert@amd.com res = list.back(); 63810234Syasuko.eckert@amd.com } else { 63910234Syasuko.eckert@amd.com delete list.back(); 64010234Syasuko.eckert@amd.com } 64110234Syasuko.eckert@amd.com list.pop_back(); 64210152Satgutier@umich.edu } 64310234Syasuko.eckert@amd.com if (!res) { 64410234Syasuko.eckert@amd.com cout << "ERROR: no valid tag organizations found" << endl; 64510234Syasuko.eckert@amd.com exit(0); 64610152Satgutier@umich.edu } 64710152Satgutier@umich.edu 64810234Syasuko.eckert@amd.com list.push_back(res); 64910152Satgutier@umich.edu} 65010152Satgutier@umich.edu 65110152Satgutier@umich.edu 65210152Satgutier@umich.edu 65310234Syasuko.eckert@amd.comvoid filter_data_arr(list<mem_array *> & curr_list) { 65410234Syasuko.eckert@amd.com if (curr_list.empty() == true) { 65510234Syasuko.eckert@amd.com cout << "ERROR: no valid data array organizations found" << endl; 65610234Syasuko.eckert@amd.com exit(1); 65710234Syasuko.eckert@amd.com } 65810152Satgutier@umich.edu 65910234Syasuko.eckert@amd.com list<mem_array *>::iterator iter; 66010152Satgutier@umich.edu 66110234Syasuko.eckert@amd.com for (iter = curr_list.begin(); iter != curr_list.end(); ++iter) { 66210234Syasuko.eckert@amd.com mem_array * m = *iter; 66310152Satgutier@umich.edu 66410234Syasuko.eckert@amd.com if (m == NULL) exit(1); 66510152Satgutier@umich.edu 66610234Syasuko.eckert@amd.com if (((m->access_time - m->arr_min->min_delay) / m->arr_min->min_delay > 66710234Syasuko.eckert@amd.com 0.5) && 66810234Syasuko.eckert@amd.com ((m->power.readOp.dynamic - m->arr_min->min_dyn) / 66910234Syasuko.eckert@amd.com m->arr_min->min_dyn > 0.5)) { 67010234Syasuko.eckert@amd.com delete m; 67110234Syasuko.eckert@amd.com iter = curr_list.erase(iter); 67210234Syasuko.eckert@amd.com iter --; 67310234Syasuko.eckert@amd.com } 67410152Satgutier@umich.edu } 67510152Satgutier@umich.edu} 67610152Satgutier@umich.edu 67710152Satgutier@umich.edu 67810152Satgutier@umich.edu 67910152Satgutier@umich.edu/* 68010152Satgutier@umich.edu * Performs exhaustive search across different sub-array sizes, 68110152Satgutier@umich.edu * wire types and aspect ratios to find an optimal UCA organization 68210152Satgutier@umich.edu * 1. First different valid tag array organizations are calculated 68310152Satgutier@umich.edu * and stored in tag_arr array 68410152Satgutier@umich.edu * 2. The exhaustive search is repeated to find valid data array 68510152Satgutier@umich.edu * organizations and stored in data_arr array 68610152Satgutier@umich.edu * 3. Cache area, delay, power, and cycle time for different 68710152Satgutier@umich.edu * cache organizations are calculated based on the 68810152Satgutier@umich.edu * above results 68910152Satgutier@umich.edu * 4. Cache model with least cost is picked from sol_list 69010152Satgutier@umich.edu */ 69110234Syasuko.eckert@amd.comvoid solve(uca_org_t *fin_res) { 69210234Syasuko.eckert@amd.com bool is_dram = false; 69310234Syasuko.eckert@amd.com int pure_ram = g_ip->pure_ram; 69410234Syasuko.eckert@amd.com bool pure_cam = g_ip->pure_cam; 69510152Satgutier@umich.edu 69610234Syasuko.eckert@amd.com init_tech_params(g_ip->F_sz_um, false); 69710152Satgutier@umich.edu 69810152Satgutier@umich.edu 69910234Syasuko.eckert@amd.com list<mem_array *> tag_arr (0); 70010234Syasuko.eckert@amd.com list<mem_array *> data_arr(0); 70110234Syasuko.eckert@amd.com list<mem_array *>::iterator miter; 70210234Syasuko.eckert@amd.com list<uca_org_t> sol_list(1, uca_org_t()); 70310152Satgutier@umich.edu 70410234Syasuko.eckert@amd.com fin_res->tag_array.access_time = 0; 70510234Syasuko.eckert@amd.com fin_res->tag_array.Ndwl = 0; 70610234Syasuko.eckert@amd.com fin_res->tag_array.Ndbl = 0; 70710234Syasuko.eckert@amd.com fin_res->tag_array.Nspd = 0; 70810234Syasuko.eckert@amd.com fin_res->tag_array.deg_bl_muxing = 0; 70910234Syasuko.eckert@amd.com fin_res->tag_array.Ndsam_lev_1 = 0; 71010234Syasuko.eckert@amd.com fin_res->tag_array.Ndsam_lev_2 = 0; 71110152Satgutier@umich.edu 71210152Satgutier@umich.edu 71310234Syasuko.eckert@amd.com // distribute calculate_time() execution to multiple threads 71410234Syasuko.eckert@amd.com calc_time_mt_wrapper_struct * calc_array = 71510234Syasuko.eckert@amd.com new calc_time_mt_wrapper_struct[nthreads]; 71610234Syasuko.eckert@amd.com pthread_t threads[nthreads]; 71710152Satgutier@umich.edu 71810234Syasuko.eckert@amd.com for (uint32_t t = 0; t < nthreads; t++) { 71910234Syasuko.eckert@amd.com calc_array[t].tid = t; 72010234Syasuko.eckert@amd.com calc_array[t].pure_ram = pure_ram; 72110234Syasuko.eckert@amd.com calc_array[t].pure_cam = pure_cam; 72210234Syasuko.eckert@amd.com calc_array[t].data_res = new min_values_t(); 72310234Syasuko.eckert@amd.com calc_array[t].tag_res = new min_values_t(); 72410152Satgutier@umich.edu } 72510152Satgutier@umich.edu 72610234Syasuko.eckert@amd.com bool is_tag; 72710234Syasuko.eckert@amd.com uint32_t ram_cell_tech_type; 72810234Syasuko.eckert@amd.com 72910234Syasuko.eckert@amd.com // If it's a cache, first calculate the area, delay and power for all tag array partitions. 73010234Syasuko.eckert@amd.com if (!(pure_ram || pure_cam || g_ip->fully_assoc)) { //cache 73110234Syasuko.eckert@amd.com is_tag = true; 73210234Syasuko.eckert@amd.com ram_cell_tech_type = g_ip->tag_arr_ram_cell_tech_type; 73310234Syasuko.eckert@amd.com is_dram = ((ram_cell_tech_type == lp_dram) || 73410234Syasuko.eckert@amd.com (ram_cell_tech_type == comm_dram)); 73510234Syasuko.eckert@amd.com init_tech_params(g_ip->F_sz_um, is_tag); 73610234Syasuko.eckert@amd.com 73710234Syasuko.eckert@amd.com for (uint32_t t = 0; t < nthreads; t++) { 73810234Syasuko.eckert@amd.com calc_array[t].is_tag = is_tag; 73910234Syasuko.eckert@amd.com calc_array[t].is_main_mem = false; 74010234Syasuko.eckert@amd.com calc_array[t].Nspd_min = 0.125; 74110234Syasuko.eckert@amd.com#ifndef DEBUG 74210234Syasuko.eckert@amd.com pthread_create(&threads[t], NULL, calc_time_mt_wrapper, 74310234Syasuko.eckert@amd.com (void *)(&(calc_array[t]))); 74410234Syasuko.eckert@amd.com#else 74510234Syasuko.eckert@amd.com calc_time_mt_wrapper((void *)(&(calc_array[t]))); 74610234Syasuko.eckert@amd.com#endif 74710234Syasuko.eckert@amd.com } 74810234Syasuko.eckert@amd.com 74910234Syasuko.eckert@amd.com#ifndef DEBUG 75010234Syasuko.eckert@amd.com for (uint32_t t = 0; t < nthreads; t++) { 75110234Syasuko.eckert@amd.com pthread_join(threads[t], NULL); 75210234Syasuko.eckert@amd.com } 75310234Syasuko.eckert@amd.com#endif 75410234Syasuko.eckert@amd.com 75510234Syasuko.eckert@amd.com for (uint32_t t = 0; t < nthreads; t++) { 75610234Syasuko.eckert@amd.com calc_array[t].data_arr.sort(mem_array::lt); 75710234Syasuko.eckert@amd.com data_arr.merge(calc_array[t].data_arr, mem_array::lt); 75810234Syasuko.eckert@amd.com calc_array[t].tag_arr.sort(mem_array::lt); 75910234Syasuko.eckert@amd.com tag_arr.merge(calc_array[t].tag_arr, mem_array::lt); 76010234Syasuko.eckert@amd.com } 76110152Satgutier@umich.edu } 76210152Satgutier@umich.edu 76310152Satgutier@umich.edu 76410234Syasuko.eckert@amd.com // calculate the area, delay and power for all data array partitions (for cache or plain RAM). 76510234Syasuko.eckert@amd.com // in the new cacti, cam, fully_associative cache are processed as single array in the data portion 76610152Satgutier@umich.edu is_tag = false; 76710152Satgutier@umich.edu ram_cell_tech_type = g_ip->data_arr_ram_cell_tech_type; 76810152Satgutier@umich.edu is_dram = ((ram_cell_tech_type == lp_dram) || (ram_cell_tech_type == comm_dram)); 76910152Satgutier@umich.edu init_tech_params(g_ip->F_sz_um, is_tag); 77010152Satgutier@umich.edu 77110234Syasuko.eckert@amd.com for (uint32_t t = 0; t < nthreads; t++) { 77210234Syasuko.eckert@amd.com calc_array[t].is_tag = is_tag; 77310234Syasuko.eckert@amd.com calc_array[t].is_main_mem = g_ip->is_main_mem; 77410234Syasuko.eckert@amd.com if (!(pure_cam || g_ip->fully_assoc)) { 77510234Syasuko.eckert@amd.com calc_array[t].Nspd_min = (double)(g_ip->out_w) / 77610234Syasuko.eckert@amd.com (double)(g_ip->block_sz * 8); 77710234Syasuko.eckert@amd.com } else { 77810234Syasuko.eckert@amd.com calc_array[t].Nspd_min = 1; 77910234Syasuko.eckert@amd.com } 78010152Satgutier@umich.edu 78110234Syasuko.eckert@amd.com#ifndef DEBUG 78210234Syasuko.eckert@amd.com pthread_create(&threads[t], NULL, calc_time_mt_wrapper, 78310234Syasuko.eckert@amd.com (void *)(&(calc_array[t]))); 78410234Syasuko.eckert@amd.com#else 78510234Syasuko.eckert@amd.com calc_time_mt_wrapper((void *)(&(calc_array[t]))); 78610234Syasuko.eckert@amd.com#endif 78710152Satgutier@umich.edu } 78810152Satgutier@umich.edu 78910234Syasuko.eckert@amd.com#ifndef DEBUG 79010234Syasuko.eckert@amd.com for (uint32_t t = 0; t < nthreads; t++) { 79110234Syasuko.eckert@amd.com pthread_join(threads[t], NULL); 79210234Syasuko.eckert@amd.com } 79310234Syasuko.eckert@amd.com#endif 79410234Syasuko.eckert@amd.com 79510234Syasuko.eckert@amd.com data_arr.clear(); 79610234Syasuko.eckert@amd.com for (uint32_t t = 0; t < nthreads; t++) { 79710234Syasuko.eckert@amd.com calc_array[t].data_arr.sort(mem_array::lt); 79810234Syasuko.eckert@amd.com data_arr.merge(calc_array[t].data_arr, mem_array::lt); 79910234Syasuko.eckert@amd.com 80010234Syasuko.eckert@amd.com 80110152Satgutier@umich.edu } 80210152Satgutier@umich.edu 80310234Syasuko.eckert@amd.com 80410234Syasuko.eckert@amd.com 80510234Syasuko.eckert@amd.com min_values_t * d_min = new min_values_t(); 80610234Syasuko.eckert@amd.com min_values_t * t_min = new min_values_t(); 80710234Syasuko.eckert@amd.com min_values_t * cache_min = new min_values_t(); 80810234Syasuko.eckert@amd.com 80910234Syasuko.eckert@amd.com for (uint32_t t = 0; t < nthreads; t++) { 81010234Syasuko.eckert@amd.com d_min->update_min_values(calc_array[t].data_res); 81110234Syasuko.eckert@amd.com t_min->update_min_values(calc_array[t].tag_res); 81210234Syasuko.eckert@amd.com } 81310234Syasuko.eckert@amd.com 81410234Syasuko.eckert@amd.com for (miter = data_arr.begin(); miter != data_arr.end(); miter++) { 81510234Syasuko.eckert@amd.com (*miter)->arr_min = d_min; 81610234Syasuko.eckert@amd.com } 81710234Syasuko.eckert@amd.com 81810234Syasuko.eckert@amd.com filter_data_arr(data_arr); 81910234Syasuko.eckert@amd.com if (!(pure_ram || pure_cam || g_ip->fully_assoc)) { 82010234Syasuko.eckert@amd.com filter_tag_arr(t_min, tag_arr); 82110234Syasuko.eckert@amd.com } 82210234Syasuko.eckert@amd.com 82310234Syasuko.eckert@amd.com if (pure_ram || pure_cam || g_ip->fully_assoc) { 82410234Syasuko.eckert@amd.com for (miter = data_arr.begin(); miter != data_arr.end(); miter++) { 82510234Syasuko.eckert@amd.com uca_org_t & curr_org = sol_list.back(); 82610234Syasuko.eckert@amd.com curr_org.tag_array2 = NULL; 82710234Syasuko.eckert@amd.com curr_org.data_array2 = (*miter); 82810234Syasuko.eckert@amd.com 82910234Syasuko.eckert@amd.com curr_org.find_delay(); 83010234Syasuko.eckert@amd.com curr_org.find_energy(); 83110234Syasuko.eckert@amd.com curr_org.find_area(); 83210234Syasuko.eckert@amd.com curr_org.find_cyc(); 83310234Syasuko.eckert@amd.com 83410234Syasuko.eckert@amd.com //update min values for the entire cache 83510234Syasuko.eckert@amd.com cache_min->update_min_values(curr_org); 83610234Syasuko.eckert@amd.com 83710234Syasuko.eckert@amd.com sol_list.push_back(uca_org_t()); 83810234Syasuko.eckert@amd.com } 83910234Syasuko.eckert@amd.com } else { 84010234Syasuko.eckert@amd.com while (tag_arr.empty() != true) { 84110234Syasuko.eckert@amd.com mem_array * arr_temp = (tag_arr.back()); 84210234Syasuko.eckert@amd.com tag_arr.pop_back(); 84310234Syasuko.eckert@amd.com 84410234Syasuko.eckert@amd.com for (miter = data_arr.begin(); miter != data_arr.end(); miter++) { 84510234Syasuko.eckert@amd.com uca_org_t & curr_org = sol_list.back(); 84610234Syasuko.eckert@amd.com curr_org.tag_array2 = arr_temp; 84710234Syasuko.eckert@amd.com curr_org.data_array2 = (*miter); 84810234Syasuko.eckert@amd.com 84910234Syasuko.eckert@amd.com curr_org.find_delay(); 85010234Syasuko.eckert@amd.com curr_org.find_energy(); 85110234Syasuko.eckert@amd.com curr_org.find_area(); 85210234Syasuko.eckert@amd.com curr_org.find_cyc(); 85310234Syasuko.eckert@amd.com 85410234Syasuko.eckert@amd.com //update min values for the entire cache 85510234Syasuko.eckert@amd.com cache_min->update_min_values(curr_org); 85610234Syasuko.eckert@amd.com 85710234Syasuko.eckert@amd.com sol_list.push_back(uca_org_t()); 85810234Syasuko.eckert@amd.com } 85910234Syasuko.eckert@amd.com } 86010234Syasuko.eckert@amd.com } 86110234Syasuko.eckert@amd.com 86210234Syasuko.eckert@amd.com sol_list.pop_back(); 86310234Syasuko.eckert@amd.com 86410234Syasuko.eckert@amd.com find_optimal_uca(fin_res, cache_min, sol_list); 86510234Syasuko.eckert@amd.com 86610234Syasuko.eckert@amd.com sol_list.clear(); 86710234Syasuko.eckert@amd.com 86810234Syasuko.eckert@amd.com for (miter = data_arr.begin(); miter != data_arr.end(); ++miter) { 86910234Syasuko.eckert@amd.com if (*miter != fin_res->data_array2) { 87010234Syasuko.eckert@amd.com delete *miter; 87110234Syasuko.eckert@amd.com } 87210234Syasuko.eckert@amd.com } 87310152Satgutier@umich.edu data_arr.clear(); 87410234Syasuko.eckert@amd.com 87510234Syasuko.eckert@amd.com for (uint32_t t = 0; t < nthreads; t++) { 87610234Syasuko.eckert@amd.com delete calc_array[t].data_res; 87710234Syasuko.eckert@amd.com delete calc_array[t].tag_res; 87810152Satgutier@umich.edu } 87910152Satgutier@umich.edu 88010234Syasuko.eckert@amd.com delete [] calc_array; 88110234Syasuko.eckert@amd.com delete cache_min; 88210234Syasuko.eckert@amd.com delete d_min; 88310234Syasuko.eckert@amd.com delete t_min; 88410152Satgutier@umich.edu} 88510152Satgutier@umich.edu 88610152Satgutier@umich.eduvoid update(uca_org_t *fin_res) 88710152Satgutier@umich.edu{ 88810152Satgutier@umich.edu if(fin_res->tag_array2) 88910152Satgutier@umich.edu { 89010152Satgutier@umich.edu init_tech_params(g_ip->F_sz_um,true); 89110234Syasuko.eckert@amd.com DynamicParameter tag_arr_dyn_p(true, g_ip->pure_ram, g_ip->pure_cam, 89210234Syasuko.eckert@amd.com fin_res->tag_array2->Nspd, 89310234Syasuko.eckert@amd.com fin_res->tag_array2->Ndwl, 89410234Syasuko.eckert@amd.com fin_res->tag_array2->Ndbl, 89510234Syasuko.eckert@amd.com fin_res->tag_array2->Ndcm, 89610234Syasuko.eckert@amd.com fin_res->tag_array2->Ndsam_lev_1, 89710234Syasuko.eckert@amd.com fin_res->tag_array2->Ndsam_lev_2, 89810234Syasuko.eckert@amd.com g_ip->is_main_mem); 89910152Satgutier@umich.edu if(tag_arr_dyn_p.is_valid) 90010152Satgutier@umich.edu { 90110152Satgutier@umich.edu UCA * tag_arr = new UCA(tag_arr_dyn_p); 90210152Satgutier@umich.edu fin_res->tag_array2->power = tag_arr->power; 90310152Satgutier@umich.edu } 90410152Satgutier@umich.edu else 90510152Satgutier@umich.edu { 90610234Syasuko.eckert@amd.com cout << "ERROR: Cannot retrieve array structure for leakage feedback" 90710234Syasuko.eckert@amd.com << endl; 90810152Satgutier@umich.edu exit(1); 90910152Satgutier@umich.edu } 91010152Satgutier@umich.edu } 91110152Satgutier@umich.edu init_tech_params(g_ip->F_sz_um,false); 91210234Syasuko.eckert@amd.com DynamicParameter data_arr_dyn_p(false, g_ip->pure_ram, g_ip->pure_cam, 91310234Syasuko.eckert@amd.com fin_res->data_array2->Nspd, 91410234Syasuko.eckert@amd.com fin_res->data_array2->Ndwl, 91510234Syasuko.eckert@amd.com fin_res->data_array2->Ndbl, 91610234Syasuko.eckert@amd.com fin_res->data_array2->Ndcm, 91710234Syasuko.eckert@amd.com fin_res->data_array2->Ndsam_lev_1, 91810234Syasuko.eckert@amd.com fin_res->data_array2->Ndsam_lev_2, 91910234Syasuko.eckert@amd.com g_ip->is_main_mem); 92010152Satgutier@umich.edu if(data_arr_dyn_p.is_valid) 92110152Satgutier@umich.edu { 92210152Satgutier@umich.edu UCA * data_arr = new UCA(data_arr_dyn_p); 92310152Satgutier@umich.edu fin_res->data_array2->power = data_arr->power; 92410152Satgutier@umich.edu } 92510152Satgutier@umich.edu else 92610152Satgutier@umich.edu { 92710234Syasuko.eckert@amd.com cout << "ERROR: Cannot retrieve array structure for leakage feedback" 92810234Syasuko.eckert@amd.com << endl; 92910152Satgutier@umich.edu exit(1); 93010152Satgutier@umich.edu } 93110152Satgutier@umich.edu 93210152Satgutier@umich.edu fin_res->find_energy(); 93310152Satgutier@umich.edu} 93410152Satgutier@umich.edu 935