Searched refs:sp (Results 76 - 80 of 80) sorted by relevance

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/gem5/src/arch/arm/kvm/
H A Darmv8_cpu.cc101 { INT_REG(regs.sp), INTREG_SP0, "SP(EL0)" },
/gem5/src/arch/mips/
H A Disa.cc251 cfg3.sp = cp.CP0_Config3_SP;
/gem5/src/arch/arm/
H A Dmiscregs_types.hh74 Bitfield<0> sp; // AArch64 member in namespace:ArmISA
H A Disa.hh484 if (!cpsr.sp && el != EL0)
H A Disa.cc1891 cpsr.sp = (uint8_t) ((CPSR) newVal).sp;

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