Searched refs:set (Results 51 - 75 of 322) sorted by relevance

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/gem5/src/base/filters/
H A Dmulti_bit_sel_bloom_filter.hh51 void set(Addr addr) override;
H A Dmulti_bloom_filter.hh55 void set(Addr addr) override;
H A Dperfect_bloom_filter.hh52 void set(Addr addr) override;
60 /** Container storing all set (seen) entries. */
/gem5/src/cpu/
H A Dtimebuf.hh66 void set(int idx) function in class:TimeBuffer::wire
87 set(i.index);
93 set(idx);
99 set(index + offset);
105 set(index - offset);
111 set(index + 1);
118 set(index + 1);
124 set(index - 1);
131 set(index - 1);
/gem5/src/arch/generic/
H A Dtypes.hh61 PCStateBase(Addr val) : _pc(0), _npc(0) { set(val); }
101 * @param val The value to set the PC to.
103 void set(Addr val);
155 set(Addr val) function in class:GenericISA::SimplePCState
168 SimplePCState(Addr val) { set(val); }
218 set(Addr val) function in class:GenericISA::UPCState
220 Base::set(val);
226 UPCState(Addr val) : _upc(0), _nupc(0) { set(val); }
307 set(Addr val) function in class:GenericISA::DelaySlotPCState
309 Base::set(va
396 set(Addr val) function in class:GenericISA::DelaySlotUPCState
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/gem5/ext/dsent/model/std_cells/
H A DBUF.cc184 cache->set(cell_name + "->ActiveArea", area);
200 cache->set(cell_name + "->Leakage->!A", leakage_0);
201 cache->set(cell_name + "->Leakage->A", leakage_1);
213 cache->set(cell_name + "->Cap->A", a_cap);
214 cache->set(cell_name + "->Cap->Y_b", y_b_cap);
215 cache->set(cell_name + "->Cap->Y", y_cap);
228 cache->set(cell_name + "->DriveRes->Y", y_ron);
229 cache->set(cell_name + "->Delay->A_to_Y", a_to_y_delay);
H A DCellMacros.cc88 cell_->getGenProperties()->set(name_ + "_GatePitches", 2 * folds);
99 cell_->getGenProperties()->set(name_ + "_LeakagePower_00", leakage_power_00);
100 cell_->getGenProperties()->set(name_ + "_LeakagePower_01", leakage_power_01);
101 cell_->getGenProperties()->set(name_ + "_LeakagePower_10", leakage_power_10);
102 cell_->getGenProperties()->set(name_ + "_LeakagePower_11", leakage_power_11);
127 cell_->getGenProperties()->set(name_ + "_ZN_Flip", zn_flip_energy);
128 cell_->getGenProperties()->set(name_ + "_A1_Flip", a1_flip_energy);
129 cell_->getGenProperties()->set(name_ + "_A2_Flip", a2_flip_energy);
188 cell_->getGenProperties()->set(name_ + "_GatePitches", 2 * folds);
199 cell_->getGenProperties()->set(name
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H A DINV.cc189 cache->set(cell_name + "->Area->Active", area);
190 cache->set(cell_name + "->Area->Metal1Wire", area);
199 cache->set(cell_name + "->Leakage->!A", leakage_a0);
200 cache->set(cell_name + "->Leakage->A", leakage_a1);
208 cache->set(cell_name + "->Event_A_Flip", event_a_flip);
218 cache->set(cell_name + "->Cap->A", a_cap);
219 cache->set(cell_name + "->Cap->Y", y_cap);
229 cache->set(cell_name + "->DriveRes->Y", y_ron);
230 cache->set(cell_name + "->Delay->A_to_Y", a_to_y_delay);
H A DAND2.cc231 cache->set(cell_name + "->ActiveArea", area);
245 cache->set(cell_name + "->Leakage->!A!B", leakage_00);
246 cache->set(cell_name + "->Leakage->!AB", leakage_01);
247 cache->set(cell_name + "->Leakage->A!B", leakage_10);
248 cache->set(cell_name + "->Leakage->AB", leakage_11);
263 cache->set(cell_name + "->Cap->A", a_cap);
264 cache->set(cell_name + "->Cap->B", b_cap);
265 cache->set(cell_name + "->Cap->Y_b", y_b_cap);
266 cache->set(cell_name + "->Cap->Y", y_cap);
282 cache->set(cell_nam
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H A DNAND2.cc220 cache->set(cell_name + "->Area->Active", area);
230 cache->set(cell_name + "->Leakage->!A!B", leakage_00);
231 cache->set(cell_name + "->Leakage->!AB", leakage_01);
232 cache->set(cell_name + "->Leakage->A!B", leakage_10);
233 cache->set(cell_name + "->Leakage->AB", leakage_11);
246 cache->set(cell_name + "->Event_A_Flip", event_a_flip);
247 cache->set(cell_name + "->Event_B_Flip", event_b_flip);
248 cache->set(cell_name + "->Event_Y_Flip", event_y_flip);
260 cache->set(cell_name + "->Cap->A", a_cap);
261 cache->set(cell_nam
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H A DNOR2.cc219 cache->set(cell_name + "->ActiveArea", area);
229 cache->set(cell_name + "->Leakage->!A!B", leakage_00);
230 cache->set(cell_name + "->Leakage->!AB", leakage_01);
231 cache->set(cell_name + "->Leakage->A!B", leakage_10);
232 cache->set(cell_name + "->Leakage->AB", leakage_11);
245 cache->set(cell_name + "->Event_A_Flip", event_a_flip);
246 cache->set(cell_name + "->Event_B_Flip", event_b_flip);
247 cache->set(cell_name + "->Event_ZN_Flip", event_zn_flip);
261 cache->set(cell_name + "->Cap->A", a_cap);
262 cache->set(cell_nam
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H A DMUX2.cc274 cache->set(cell_name + "->ActiveArea", area);
330 cache->set(cell_name + "->Leakage->!A!B!S0", leakage_000);
331 cache->set(cell_name + "->Leakage->!A!BS0", leakage_001);
332 cache->set(cell_name + "->Leakage->!AB!S0", leakage_010);
333 cache->set(cell_name + "->Leakage->!ABS0", leakage_011);
334 cache->set(cell_name + "->Leakage->A!B!S0", leakage_100);
335 cache->set(cell_name + "->Leakage->A!BS0", leakage_101);
336 cache->set(cell_name + "->Leakage->AB!S0", leakage_110);
337 cache->set(cell_name + "->Leakage->ABS0", leakage_111);
351 cache->set(cell_nam
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H A DLATQ.cc273 cache->set(cell_name + "->Area->Active", area);
274 cache->set(cell_name + "->Area->Metal1Wire", area); //Cover-block m1 area
332 cache->set(cell_name + "->Leakage->!D!G!Q", leakage_000);
333 cache->set(cell_name + "->Leakage->!D!GQ", leakage_001);
334 cache->set(cell_name + "->Leakage->!DG!Q", leakage_010);
335 cache->set(cell_name + "->Leakage->D!G!Q", leakage_100);
336 cache->set(cell_name + "->Leakage->D!GQ", leakage_101);
337 cache->set(cell_name + "->Leakage->DGQ", leakage_111);
357 cache->set(cell_name + "->Cap->D", d_cap);
358 cache->set(cell_nam
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/gem5/util/
H A Dcheckpoint_aggregator.py75 merged_config.set(newsec, item[0], int(item[1]) + (page_ptr << 12))
77 merged_config.set(newsec, item[0], item[1])
80 merged_config.set(newsec, "M5_pid", i)
92 merged_config.set(sec, item[0], item[1])
118 merged_config.set("system", "pagePtr", page_ptr)
119 merged_config.set("system", "nextPID", len(cpts))
134 merged_config.set("system.physmem.store0", "range_size", page_ptr * 4 * 1024)
137 merged_config.set("Globals", "curTick", max_curtick)
/gem5/src/base/
H A Dinet.hh289 void set(const EthPacketPtr &ptr) function in class:Net::IpPtr
305 IpPtr(const EthPacketPtr &ptr) : p(0), eth_hdr_vlan(false) { set(ptr); }
306 IpPtr(const EthPtr &ptr) : p(0), eth_hdr_vlan(false) { set(ptr.p); }
320 const IpPtr &operator=(const EthPacketPtr &ptr) { set(ptr); return *this; }
321 const IpPtr &operator=(const EthPtr &ptr) { set(ptr.p); return *this; }
402 void set(const EthPacketPtr &ptr) function in class:Net::Ip6Ptr
418 Ip6Ptr(const EthPacketPtr &ptr) : p(0), eth_hdr_vlan(false) { set(ptr); }
419 Ip6Ptr(const EthPtr &ptr) : p(0), eth_hdr_vlan(false) { set(ptr.p); }
434 { set(ptr); return *this; }
436 { set(pt
541 void set(const EthPacketPtr &ptr, int offset) { p = ptr; _off = offset; } function in class:Net::TcpPtr
542 void set(const IpPtr &ptr) function in class:Net::TcpPtr
549 void set(const Ip6Ptr &ptr) function in class:Net::TcpPtr
637 void set(const EthPacketPtr &ptr, int offset) { p = ptr; _off = offset; } function in class:Net::UdpPtr
638 void set(const IpPtr &ptr) function in class:Net::UdpPtr
645 void set(const Ip6Ptr &ptr) function in class:Net::UdpPtr
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/gem5/src/mem/ruby/common/
H A DConsumer.hh39 #include <set>
77 std::set<Tick> m_scheduled_wakeups;
/gem5/src/mem/ruby/structures/
H A DAbstractReplacementPolicy.cc71 AbstractReplacementPolicy::getLastAccess(int64_t set, int64_t way) argument
73 return m_last_ref_ptr[set][way];
/gem5/src/systemc/ext/dt/fx/
H A Dscfx_other_defs.hh206 set(i, v.get_bit(i));
221 set(i, v.get_bit(i));
236 set(i, v.get_bit(i));
251 set (i, v.get_bit(i));
272 set(i, v.get_bit(i));
287 set(i, v.get_bit(i));
302 set(i, v.get_bit(i));
317 set(i, v.get_bit(i));
/gem5/ext/testlib/
H A Dsuite.py52 tags = set()
62 self.tags = self.tags | set(tags)
/gem5/src/systemc/tlm_core/2/quantum/
H A Dglobal_quantum_python.cc45 .def("set", &tlm::tlm_global_quantum::set)
/gem5/ext/systemc/src/tlm_utils/
H A Dtlm_quantumkeeper.h49 tlm::tlm_global_quantum::instance().set(t);
81 virtual void set(const sc_core::sc_time& t) function in class:tlm_utils::tlm_quantumkeeper
108 // Non-virtual convenience method to set the local time and sync only if needed
112 set(t);
156 // global quantum into account. It's local quantum should not be set to a
/gem5/ext/pybind11/tests/
H A Dpybind11_tests.h36 void set(int set) { i = set; } argument
/gem5/src/systemc/ext/tlm_utils/
H A Dtlm_quantumkeeper.h46 tlm::tlm_global_quantum::instance().set(t);
70 virtual void set(const sc_core::sc_time &t) { m_local_time = t; } function in class:tlm_utils::tlm_quantumkeeper
91 // Non-virtual convenience method to set the local time and sync only if
96 set(t);
136 // global quantum into account. It's local quantum should not be set to a
/gem5/src/arch/arm/kvm/
H A Dgic.cc341 Addr set, clear; local
360 set = GicV2::GICD_ISENABLER.start();
364 copyBankedDistRange(from, to, set, 4);
366 set += 4, clear += 4, size -= 4;
368 copyDistRange(from, to, set, size);
371 set = GicV2::GICD_ISPENDR.start();
375 copyBankedDistRange(from, to, set, 4);
377 set += 4, clear += 4, size -= 4;
379 copyDistRange(from, to, set, size);
382 set
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/gem5/src/mem/cache/prefetch/
H A Dstride.cc123 for (int set = 0; set < sets; set++) {
124 entries[set].resize(assoc);
127 entries[set][way].setPosition(set, way);
130 entries[set][way].replacementData =
232 int set = pcHash(pc); local
236 for (auto& entry : entries[set]) {
253 int set local
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