| /gem5/src/mem/ |
| H A D | bridge.hh | 198 bool recvTimingReq(PacketPtr pkt);
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| H A D | mem_delay.hh | 109 bool recvTimingReq(PacketPtr pkt) override;
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| H A D | serial_link.hh | 190 bool recvTimingReq(PacketPtr pkt);
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| H A D | coherent_xbar.hh | 112 recvTimingReq(PacketPtr pkt) override
114 return xbar.recvTimingReq(pkt, id);
302 bool recvTimingReq(PacketPtr pkt, PortID slave_port_id);
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| H A D | dramsim2.cc | 178 DRAMSim2::recvTimingReq(PacketPtr pkt) function in class:DRAMSim2
383 DRAMSim2::MemoryPort::recvTimingReq(PacketPtr pkt) function in class:DRAMSim2::MemoryPort
386 return memory.recvTimingReq(pkt);
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| H A D | addr_mapper.cc | 107 AddrMapper::recvTimingReq(PacketPtr pkt) function in class:AddrMapper
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| H A D | mem_delay.cc | 139 MemDelay::SlavePort::recvTimingReq(PacketPtr pkt) function in class:MemDelay::SlavePort
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| H A D | dram_ctrl.hh | 121 bool recvTimingReq(PacketPtr);
1204 bool recvTimingReq(PacketPtr pkt);
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| H A D | bridge.cc | 146 Bridge::BridgeSlavePort::recvTimingReq(PacketPtr pkt) function in class:Bridge::BridgeSlavePort
148 DPRINTF(Bridge, "recvTimingReq: %s addr 0x%x\n",
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| H A D | mem_checker_monitor.cc | 135 MemCheckerMonitor::recvTimingReq(PacketPtr pkt) function in class:MemCheckerMonitor
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| H A D | noncoherent_xbar.cc | 102 NoncoherentXBar::recvTimingReq(PacketPtr pkt, PortID slave_port_id) function in class:NoncoherentXBar
116 DPRINTF(NoncoherentXBar, "recvTimingReq: src %s %s 0x%x BUSY\n",
121 DPRINTF(NoncoherentXBar, "recvTimingReq: src %s %s 0x%x\n",
150 DPRINTF(NoncoherentXBar, "recvTimingReq: src %s %s 0x%x RETRY\n",
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| H A D | serial_link.cc | 165 SerialLink::SerialLinkSlavePort::recvTimingReq(PacketPtr pkt) function in class:SerialLink::SerialLinkSlavePort
167 DPRINTF(SerialLink, "recvTimingReq: %s addr 0x%x\n",
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| /gem5/src/learning_gem5/part2/ |
| H A D | simple_cache.hh | 128 bool recvTimingReq(PacketPtr pkt) override;
176 * master port (causing recvTimingReq to be called on the slave
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| H A D | simple_memobj.cc | 100 SimpleMemobj::CPUSidePort::recvTimingReq(PacketPtr pkt) function in class:SimpleMemobj::CPUSidePort
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| /gem5/src/mem/qos/ |
| H A D | mem_sink.cc | 120 MemSinkCtrl::recvTimingReq(PacketPtr pkt) function in class:QoS::MemSinkCtrl
380 MemSinkCtrl::MemoryPort::recvTimingReq(PacketPtr pkt) function in class:QoS::MemSinkCtrl::MemoryPort
382 return memory.recvTimingReq(pkt);
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| /gem5/src/gpu-compute/ |
| H A D | tlb_coalescer.hh | 167 virtual bool recvTimingReq(PacketPtr pkt);
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| H A D | lds_state.hh | 164 recvTimingReq(PacketPtr pkt);
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| H A D | lds_state.cc | 180 LdsState::CuSidePort::recvTimingReq(PacketPtr packet) function in class:LdsState::CuSidePort
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| H A D | gpu_tlb.hh | 270 virtual bool recvTimingReq(PacketPtr pkt);
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| /gem5/src/mem/cache/ |
| H A D | noncoherent_cache.cc | 138 NoncoherentCache::recvTimingReq(PacketPtr pkt) function in class:NoncoherentCache
146 BaseCache::recvTimingReq(pkt);
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| H A D | base.hh | 297 virtual bool recvTimingReq(PacketPtr pkt) override;
504 virtual void recvTimingReq(PacketPtr pkt);
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| /gem5/ext/sst/ |
| H A D | ExtSlave.cc | 99 ExtSlave::recvTimingReq(PacketPtr pkt) function in class:ExtSlave
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| /gem5/src/mem/ruby/system/ |
| H A D | RubyPort.cc | 193 RubyPort::PioSlavePort::recvTimingReq(PacketPtr pkt) function in class:RubyPort::PioSlavePort
234 RubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt) function in class:RubyPort::MemSlavePort
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| /gem5/util/tlm/src/ |
| H A D | sc_slave_port.cc | 176 SCSlavePort::recvTimingReq(PacketPtr packet) function in class:Gem5SystemC::SCSlavePort
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| /gem5/src/dev/arm/ |
| H A D | smmu_v3_slaveifc.cc | 140 SMMUv3SlaveInterface::recvTimingReq(PacketPtr pkt) function in class:SMMUv3SlaveInterface
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